| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 345 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
346 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
348 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
371 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
372 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
373 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
472 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
474 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
936 unsigned SubIdx; variable
940 : TRI(tri), Reg(reg), SubIdx(subidx) {} in TRI()
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| D | TargetInstrInfo.h | 126 unsigned &SubIdx) const { in isCoalescableExtInstr() argument
208 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
228 unsigned DestReg, unsigned SubIdx,
285 unsigned SubIdx; member
287 unsigned SubIdx = 0)
288 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
350 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
355 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
360 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
366 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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| D | CodeGenRegisters.cpp | 469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
470 if (!SubIdx) in computeSecondarySubRegs()
473 NewIdx->addComposite(SI->first, SubIdx); in computeSecondarySubRegs()
899 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses() argument
901 auto FindI = SuperRegClasses.find(SubIdx); in getSuperRegClasses()
1555 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1556 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1557 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; in pruneUnitSets()
1560 if (SuperIdx == SubIdx) in pruneUnitSets()
1569 DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx in pruneUnitSets()
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| /external/llvm/lib/Target/R600/ |
| D | SIMachineFunctionInfo.cpp | 40 unsigned SubIdx) { in getSpilledReg() argument
46 Offset += SubIdx * 4; in getSpilledReg()
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| D | SIMachineFunctionInfo.h | 48 unsigned SubIdx);
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| D | SILoadStoreOptimizer.cpp | 74 unsigned SubIdx);
198 unsigned SubIdx) { in updateRegDefsUses() argument
203 O.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
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| D | SIRegisterInfo.h | 77 unsigned SubIdx) const;
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| D | SIInstrInfo.h | 33 unsigned SubIdx,
39 unsigned SubIdx,
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 318 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
319 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
333 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
343 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
369 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
446 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
449 Copy->getOperand(0).setSubReg(SubIdx); in INITIALIZE_PASS_DEPENDENCY()
1280 if (RegSeqInput.SubIdx == DefSubReg) { in getNextSourceFromRegSequence()
1325 if (InsertedReg.SubIdx == DefSubReg) { in getNextSourceFromInsertSubreg()
1346 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0) in getNextSourceFromInsertSubreg()
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| D | ExpandPostRAPseudos.cpp | 90 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
92 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
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| D | TargetInstrInfo.cpp | 286 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
289 if (!SubIdx) { in getStackSlotRange()
295 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); in getStackSlotRange()
301 int BitOffset = TRI->getSubRegIdxOffset(SubIdx); in getStackSlotRange()
319 unsigned SubIdx, in reMaterialize() argument
323 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
920 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
946 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getInsertSubregInputs()
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| D | TargetRegisterInfo.cpp | 48 if (SubIdx) { in print()
50 OS << ':' << TRI->getSubRegIndexName(SubIdx); in print()
52 OS << ":sub(" << SubIdx << ')'; in print()
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| D | MachineInstr.cpp | 69 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg() argument
72 if (SubIdx && getSubReg()) in substVirtReg()
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
75 if (SubIdx) in substVirtReg()
76 setSubReg(SubIdx); in substVirtReg()
1099 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect() local
1101 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
1103 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); in getRegClassConstraintEffect()
1325 unsigned SubIdx, in substituteRegister() argument
1328 if (SubIdx) in substituteRegister()
[all …]
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| D | MachineCopyPropagation.cpp | 121 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy() local
122 if (!SubIdx) in isNopCopy()
124 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); in isNopCopy()
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| D | RegisterCoalescer.cpp | 207 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
1127 unsigned SubIdx) { in updateRegDefsUses() argument
1151 if (DstInt && !Reads && SubIdx) in updateRegDefsUses()
1161 if (SubIdx && MO.isDef()) in updateRegDefsUses()
1166 if (SubIdx != 0 && MO.isUse() && MRI->shouldTrackSubRegLiveness(DstReg)) { in updateRegDefsUses()
1172 unsigned Mask = TRI->getSubRegIndexLaneMask(SubIdx); in updateRegDefsUses()
1201 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
1588 const unsigned SubIdx; member in __anona927d7ac0211::JoinVals
1743 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, unsigned LaneMask, in JoinVals() argument
1747 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
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| D | LiveDebugVariables.h | 48 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
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| D | MachineVerifier.cpp | 892 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
895 if (SubIdx) { in visitMachineOperand()
910 if (SubIdx) { in visitMachineOperand()
912 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
916 << " does not support subreg index " << SubIdx << "\n"; in visitMachineOperand()
922 << " does not fully support subreg index " << SubIdx << "\n"; in visitMachineOperand()
928 if (SubIdx) { in visitMachineOperand()
935 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 440 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
443 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
456 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
489 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
498 SubIdx == DefSubIdx && in EmitSubregNode()
513 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
523 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
530 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
547 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
568 MIB.addImm(SubIdx); in EmitSubregNode()
[all …]
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| D | InstrEmitter.h | 86 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
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| /external/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, in emitLoadConstPool() argument
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
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| D | ThumbRegisterInfo.h | 42 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 158 unsigned &SubIdx) const { in isCoalescableExtInstr()
165 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
661 unsigned SubIdx; in insertSelect() local
665 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
666 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
667 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
668 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
669 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
670 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
671 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 191 unsigned &SubIdx) const override;
212 unsigned DestReg, unsigned SubIdx,
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