Searched refs:SubReg0 (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 203 unsigned Src0 = 0, SubReg0; in isProfitableToTransform() local
209 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform()
296 unsigned Src0 = 0, SubReg0; in transformInstruction() local
302 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction()
327 SubReg0 = 0; in transformInstruction()
346 .addReg(Src0, getKillRegState(true), SubReg0) in transformInstruction()
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 140 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0; in commuteInstruction() local
151 SubReg0 = SubReg2; in commuteInstruction()
156 SubReg0 = SubReg1; in commuteInstruction()
167 MI->getOperand(0).setSubReg(SubReg0); in commuteInstruction()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1568 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32); in createGPRPairNode() local
1570 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1579 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); in createSRegPairNode() local
1581 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1589 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); in createDRegPairNode() local
1591 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1599 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); in createQRegPairNode() local
1601 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1611 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); in createQuadSRegsNode() local
1615 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
[all …]
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelDAGToDAG.cpp | 376 SDValue RC, SubReg0, SubReg1; in Select() local
382 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32); in Select()
386 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32); in Select()
391 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0, in Select()
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