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Searched refs:TGSI_OPCODE_INEG (Results 1 – 8 of 8) sorted by relevance

/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_info.c163 { 1, 1, 0, 0, 0, 0, COMP, "INEG", TGSI_OPCODE_INEG },
299 case TGSI_OPCODE_INEG: in tgsi_opcode_infer_src_type()
347 case TGSI_OPCODE_INEG: in tgsi_opcode_infer_dst_type()
Dtgsi_exec.c4069 case TGSI_OPCODE_INEG: in exec_instruction()
/external/mesa3d/src/gallium/include/pipe/
Dp_shader_tokens.h373 #define TGSI_OPCODE_INEG 123 macro
/external/mesa3d/src/gallium/drivers/nv50/codegen/
Dnv50_ir_from_tgsi.cpp388 case TGSI_OPCODE_INEG: in inferSrcType()
1798 case TGSI_OPCODE_INEG: in handleInstruction()
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_tgsi_action.c1582 bld_base->op_actions[TGSI_OPCODE_INEG].emit = ineg_emit_cpu; in lp_set_default_actions_cpu()
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_setup_tgsi_llvm.c1066 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg; in radeon_llvm_context_init()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_shader.c5372 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
5546 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
5720 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
/external/mesa3d/src/mesa/state_tracker/
Dst_glsl_to_tgsi.cpp1417 emit(ir, TGSI_OPCODE_INEG, result_dst, op[0]); in visit()
1810 emit(ir, TGSI_OPCODE_INEG, result_dst, op[0]); in visit()