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Searched refs:TGSI_OPCODE_SSG (Results 1 – 16 of 16) sorted by relevance

/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_util.c212 case TGSI_OPCODE_SSG: in tgsi_util_get_inst_usage_mask()
Dtgsi_info.c105 { 1, 1, 0, 0, 0, 0, COMP, "SSG", TGSI_OPCODE_SSG },
Dtgsi_exec.c3805 case TGSI_OPCODE_SSG: in exec_instruction()
/external/mesa3d/src/gallium/include/pipe/
Dp_shader_tokens.h322 #define TGSI_OPCODE_SSG 65 /* SGN */ macro
/external/mesa3d/src/gallium/drivers/r300/
Dr300_tgsi_to_rc.c98 case TGSI_OPCODE_SSG: return RC_OPCODE_SSG; in translate_opcode()
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_setup_tgsi_llvm.c1070 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg; in radeon_llvm_context_init()
1154 bld_base->op_actions[TGSI_OPCODE_SSG].emit = build_tgsi_intrinsic_nomem; in radeon_llvm_context_init()
1155 bld_base->op_actions[TGSI_OPCODE_SSG].intr_name = "llvm.AMDGPU.ssg"; in radeon_llvm_context_init()
/external/mesa3d/src/mesa/state_tracker/
Dst_mesa_to_tgsi.c645 return TGSI_OPCODE_SSG; in translate_opcode()
Dst_glsl_to_tgsi.cpp1427 emit(ir, TGSI_OPCODE_SSG, result_dst, op[0]); in visit()
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_tgsi_aos.c801 case TGSI_OPCODE_SSG: in lp_emit_instruction_aos()
Dlp_bld_tgsi_action.c1608 bld_base->op_actions[TGSI_OPCODE_SSG].emit = ssg_emit_cpu; in lp_set_default_actions_cpu()
/external/mesa3d/src/gallium/drivers/i915/
Di915_fpc_translate.c1022 case TGSI_OPCODE_SSG: in i915_translate_instruction()
/external/mesa3d/src/gallium/drivers/svga/
Dsvga_tgsi_insn.c2693 case TGSI_OPCODE_SSG: in svga_emit_instruction()
3114 emit->info.opcode_count[TGSI_OPCODE_SSG] >= 1 || in needs_to_create_zero()
/external/mesa3d/src/gallium/drivers/nv30/
Dnvfx_vertprog.c677 case TGSI_OPCODE_SSG: in nvfx_vertprog_parse_instruction()
Dnvfx_fragprog.c748 case TGSI_OPCODE_SSG: in nvfx_fragprog_parse_instruction()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_shader.c5308 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
5482 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
5656 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
/external/mesa3d/src/gallium/drivers/nv50/codegen/
Dnv50_ir_from_tgsi.cpp1948 case TGSI_OPCODE_SSG: in handleInstruction()