Searched refs:TGSI_OPCODE_UMIN (Results 1 – 7 of 7) sorted by relevance
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 173 { 1, 2, 0, 0, 0, 0, COMP, "UMIN", TGSI_OPCODE_UMIN },
285 case TGSI_OPCODE_UMIN: in tgsi_opcode_infer_src_type()
333 case TGSI_OPCODE_UMIN: in tgsi_opcode_infer_dst_type()
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| D | tgsi_exec.c | 4109 case TGSI_OPCODE_UMIN: in exec_instruction()
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| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 383 #define TGSI_OPCODE_UMIN 133 macro
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_setup_tgsi_llvm.c | 1096 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem; in radeon_llvm_context_init()
1097 bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin"; in radeon_llvm_context_init()
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 375 case TGSI_OPCODE_UMIN: in inferSrcType()
1763 case TGSI_OPCODE_UMIN: in handleInstruction()
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_action.c | 1617 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = umin_emit_cpu; in lp_set_default_actions_cpu()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 5382 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
5556 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
5730 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
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