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Searched refs:TMP1 (Results 1 – 23 of 23) sorted by relevance

/external/pcre/dist/
Dpcre_jit_compile.c478 #define TMP1 SLJIT_R0 macro
1444 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(0)); in init_frame()
1447 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
1460 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->mark_ptr); in init_frame()
1463 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
1473 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(0)); in init_frame()
1476 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
1482 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->mark_ptr); in init_frame()
1485 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
1491 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->capture_last_ptr); in init_frame()
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dppc64le-localentry.ll20 ; CHECK-NEXT: .Ltmp[[TMP1:[0-9]+]]:
21 ; CHECK-NEXT: addis 2, 12, .TOC.-.Ltmp[[TMP1]]@ha
22 ; CHECK-NEXT: addi 2, 2, .TOC.-.Ltmp[[TMP1]]@l
24 ; CHECK-NEXT: .localentry use_toc, .Ltmp[[TMP2]]-.Ltmp[[TMP1]]
37 ; CHECK-NEXT: .Ltmp[[TMP1:[0-9]+]]:
38 ; CHECK-NEXT: addis 2, 12, .TOC.-.Ltmp[[TMP1]]@ha
39 ; CHECK-NEXT: addi 2, 2, .TOC.-.Ltmp[[TMP1]]@l
41 ; CHECK-NEXT: .localentry use_toc_implicit, .Ltmp[[TMP2]]-.Ltmp[[TMP1]]
/external/llvm/test/CodeGen/Mips/
Dselect.ll642 ; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
643 ; 32: c.eq.d $[[TMP]], $[[TMP1]]
652 ; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
653 ; 32R2: c.eq.d $[[TMP]], $[[TMP1]]
662 ; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
663 ; 32R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
675 ; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
676 ; 64: c.eq.d $[[TMP]], $[[TMP1]]
685 ; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
686 ; 64R2: c.eq.d $[[TMP]], $[[TMP1]]
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-large-frame.ll22 ; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
23 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3344
30 ; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
31 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3328
Darm64-convert-v4f64.ll26 ; CHECK-DAG: xtn v[[TMP1:[0-9]+]].4h, v[[NA0]].4s
27 ; CHECK-DAG: xtn2 v[[TMP1]].8h, v[[NA2]].4s
28 ; CHECK: xtn v0.8b, v[[TMP1]].8h
/external/jpeg/
Djsimd_arm_neon.S390 TMP1 .req r0
451 ldmia OUTPUT_BUF, {TMP1, TMP2, TMP3, TMP4}
452 add TMP1, TMP1, OUTPUT_COL
461 vst1.32 {d26[0]}, [TMP1]!
466 vst1.8 {d26[0]}, [TMP1]!
468 vst1.8 {d26[1]}, [TMP1]!
470 vst1.8 {d26[2]}, [TMP1]!
472 vst1.8 {d26[3]}, [TMP1]!
492 .unreq TMP1
551 TMP1 .req r0
[all …]
/external/llvm/test/Transforms/InstCombine/
Dzext-bool-add-sub.ll7 ; CHECK: [[TMP1:%.*]] = sext i1 %y to i32
9 ; CHECK-NEXT: add nsw i32 [[TMP2]], [[TMP1]]
/external/llvm/test/CodeGen/R600/
Dmad-combine.ll395 ; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
396 ; SI-STD: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP1]]
402 ; SI-DENORM-SLOWFMAF: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
403 ; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT1:v[0-9]+]], [[C]], [[TMP1]]
440 ; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
441 ; SI-STD: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[A]]
447 ; SI-DENORM-SLOWFMAF: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
448 ; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[A]]
491 ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[B]], [[A]]
492 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP0]], [[TMP1]]
[all …]
Dbswap.ll15 ; SI-DAG: v_alignbit_b32 [[TMP1:v[0-9]+]], [[VAL]], [[VAL]], 24
17 ; SI: v_bfi_b32 [[RESULT:v[0-9]+]], [[K]], [[TMP1]], [[TMP0]]
Dllvm.AMDGPU.bfe.i32.ll428 ; SI: v_add_i32_e32 [[TMP1:v[0-9]+]], [[TMP0]], [[BFE]]
429 ; SI: v_ashrrev_i32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]]
/external/llvm/test/MC/ARM/
Dltorg.s36 @ CHECK: ldr r0, .Ltmp[[TMP1:[0-9+]]]
43 @ CHECK: .Ltmp[[TMP1]]
Dldr-pseudo.s26 @ CHECK: ldr r0, .Ltmp[[TMP1:[0-9]+]]
165 @ CHECK: .Ltmp[[TMP1]]
/external/llvm/test/CodeGen/WinEH/
Dcppeh-nonalloca-frame-values.ll103 ; CHECK: [[TMP1:\%.+]] = load i32, i32* [[A_RELOAD]], align 8
104 ; CHECK: [[ADD:\%.+]] = add nsw i32 [[TMP1]], [[I_RELOAD]]
221 ; CHECK: [[TMP1:\%.+]] = load i32, i32* [[B_RELOAD]], align 4
222 ; CHECK: [[ADD:\%.+]] = add nsw i32 [[TMP1]], [[I_RELOAD]]
Dcppeh-nested-1.ll141 ; CHECK: [[TMP1:\%.+]] = load i32, i32* [[I_PTR]], align 4
142 ; CHECK: invoke void @"\01?handle_int@@YAXH@Z"(i32 [[TMP1]])
Dcppeh-inalloca.ll116 ; CHECK: [[TMP1:\%.+]] = load i32, i32* [[RETVAL]]
117 ; CHECK: ret i32 [[TMP1]]
Dcppeh-catch-unwind.ll38 ; CHECK: [[TMP1:\%.+]] = alloca i32, align 4
39 ; CHECK: call void (...) @llvm.frameescape(i32* [[TMP1]], %class.SomeClass* [[OBJ_PTR]], i32* [[T…
Dcppeh-multi-catch.ll169 ; CHECK: [[TMP1:\%.+]] = load i32, i32* [[I_PTR]], align 4
170 ; CHECK: call void @"\01?handle_int@@YAXH@Z"(i32 [[TMP1]])
Dcppeh-nested-3.ll190 ; CHECK: [[TMP1:\%.+]] = load i32, i32* [[I_PTR]], align 4
191 ; CHECK: invoke void @"\01?handle_int@@YAXH@Z"(i32 [[TMP1]])
Dcppeh-frame-vars.ll212 ; CHECK: [[TMP1:\%.+]] = load i32, i32* [[NUMEXCEPTIONS_PTR]], align 4
213 ; CHECK: [[IDXPROM:\%.+]] = sext i32 [[TMP1]] to i64
Dcppeh-nested-2.ll258 ; CHECK: [[TMP1:\%.+]] = load i32, i32* [[I_PTR]], align 4
259 ; CHECK: invoke void @_Z10handle_inti(i32 [[TMP1]])
/external/llvm/test/Transforms/NaryReassociate/
Dnary-add.ll170 ; CHECK: call void @foo(i32 [[TMP1:%[a-zA-Z0-9]]])
174 ; CHECK: [[TMP2:%[a-zA-Z0-9]]] = add i32 [[TMP1]], %d
/external/clang/test/CodeGenObjC/
Ddebug-info-block-captured-self.m60 // CHECK: %[[TMP1:.*]] = bitcast
/external/llvm/test/CodeGen/X86/
Dwiden_load-2.ll194 ; CHECK-NEXT: movl (%[[PTR0]]), [[TMP1:%e[abcd]+x]]
195 ; CHECK-NEXT: movl [[TMP1]], [[TMP2:.*]]