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Searched refs:TMP2 (Results 1 – 16 of 16) sorted by relevance

/external/pcre/dist/
Dpcre_jit_compile.c479 #define TMP2 SLJIT_R2 macro
1518 OP1(SLJIT_MOV, TMP2, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(offset + 1)); in init_frame()
1521 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP2, 0); in init_frame()
1688 OP1(SLJIT_MOV, TMP2, 0, SLJIT_MEM1(STACK_TOP), stackptr); in copy_private_data()
1906 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackptr, TMP2, 0); in copy_private_data()
1909 OP1(SLJIT_MOV, TMP2, 0, SLJIT_MEM1(SLJIT_SP), srcw[count]); in copy_private_data()
1931 OP1(SLJIT_MOV, SLJIT_MEM1(SLJIT_SP), srcw[count], TMP2, 0); in copy_private_data()
1935 OP1(SLJIT_MOV, TMP2, 0, SLJIT_MEM1(STACK_TOP), stackptr); in copy_private_data()
1956 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackptr, TMP2, 0); in copy_private_data()
1964 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackptr, TMP2, 0); in copy_private_data()
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dppc64le-localentry.ll23 ; CHECK-NEXT: .Ltmp[[TMP2:[0-9]+]]:
24 ; CHECK-NEXT: .localentry use_toc, .Ltmp[[TMP2]]-.Ltmp[[TMP1]]
40 ; CHECK-NEXT: .Ltmp[[TMP2:[0-9]+]]:
41 ; CHECK-NEXT: .localentry use_toc_implicit, .Ltmp[[TMP2]]-.Ltmp[[TMP1]]
/external/jpeg/
Djsimd_arm_neon.S391 TMP2 .req r1
451 ldmia OUTPUT_BUF, {TMP1, TMP2, TMP3, TMP4}
453 add TMP2, TMP2, OUTPUT_COL
463 vst1.32 {d26[1]}, [TMP2]!
475 vst1.8 {d26[4]}, [TMP2]!
477 vst1.8 {d26[5]}, [TMP2]!
479 vst1.8 {d26[6]}, [TMP2]!
481 vst1.8 {d26[7]}, [TMP2]!
493 .unreq TMP2
552 TMP2 .req ip
[all …]
/external/llvm/test/Transforms/InstCombine/
Dzext-bool-add-sub.ll8 ; CHECK: [[TMP2:%.*]] = select i1 %x, i32 2, i32 1
9 ; CHECK-NEXT: add nsw i32 [[TMP2]], [[TMP1]]
/external/llvm/test/MC/ARM/
Dltorg.s51 @ CHECK: ldr r0, .Ltmp[[TMP2:[0-9+]]]
57 @ CHECK: .Ltmp[[TMP2]]
Dldr-pseudo.s32 @ CHECK: ldr r0, .Ltmp[[TMP2:[0-9]+]]
167 @ CHECK: .Ltmp[[TMP2]]
/external/llvm/test/Transforms/NaryReassociate/
Dnary-add.ll174 ; CHECK: [[TMP2:%[a-zA-Z0-9]]] = add i32 [[TMP1]], %d
176 ; CHECK: call void @foo(i32 [[TMP2]]
/external/llvm/test/CodeGen/WinEH/
Dcppeh-nested-1.ll160 ; CHECK: [[TMP2:\%.+]] = load float, float* [[F_PTR1]], align 4
161 ; CHECK: call void @"\01?handle_float@@YAXM@Z"(float [[TMP2]])
Dcppeh-inalloca.ll159 ; CHECK: [[TMP2:\%.+]] = load i32, i32* [[A1]], align 4
161 ; CHECK: [[ADD:\%.+]] = add nsw i32 [[TMP2]], [[TMP3]]
Dcppeh-multi-catch.ll178 ; CHECK: [[TMP2:\%.+]] = load i64, i64* [[LL_PTR]], align 8
179 ; CHECK: call void @"\01?handle_long_long@@YAX_J@Z"(i64 [[TMP2]])
Dcppeh-nested-3.ll216 ; CHECK: [[TMP2:\%.+]] = load float, float* [[F_PTR]], align 4
217 ; CHECK: call void @"\01?handle_float@@YAXM@Z"(float [[TMP2]])
Dcppeh-frame-vars.ll216 ; CHECK: [[TMP2:\%.+]] = load i32, i32* [[NUMEXCEPTIONS_PTR1]], align 4
217 ; CHECK: [[INC:\%.+]] = add nsw i32 [[TMP2]], 1
Dcppeh-nonalloca-frame-values.ll227 ; CHECK: [[TMP2:\%.+]] = load i32, i32* [[A_RELOAD]], align 8
228 ; CHECK: [[ADD2:\%.+]] = add nsw i32 [[TMP2]], [[TMP]]
/external/llvm/test/CodeGen/X86/
Dwiden_load-2.ll195 ; CHECK-NEXT: movl [[TMP1]], [[TMP2:.*]]
196 ; CHECK-NEXT: pmovzxbd [[TMP2]], %[[X0:xmm[0-9]+]]
/external/llvm/test/CodeGen/R600/
Dmad-combine.ll492 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP0]], [[TMP1]]
493 ; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP2]]
538 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP0]], [[TMP1]]
539 ; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP2]], [[A]]
Dllvm.AMDGPU.bfe.i32.ll429 ; SI: v_ashrrev_i32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]]
430 ; SI: buffer_store_dword [[TMP2]]