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Searched refs:TRN1 (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h103 TRN1, enumerator
DAArch64ISelLowering.cpp827 case AArch64ISD::TRN1: return "AArch64ISD::TRN1"; in getTargetNodeName()
5093 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
5259 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; in LowerVECTOR_SHUFFLE()
5272 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; in LowerVECTOR_SHUFFLE()
DAArch64InstrInfo.td180 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
3439 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
/external/vixl/doc/
Dsupported-instructions.md3972 ### TRN1 ### subsection