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Searched refs:TSFlags (Results 1 – 25 of 59) sorted by relevance

123

/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp148 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
156 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
163 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
185 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { in isCDisp8() argument
186 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && in isCDisp8()
190 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isCDisp8()
210 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
211 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
212 bool isPCRel = X86II::isImmPCRel(TSFlags); in getImmFixupKind()
214 if (X86II::isImmSigned(TSFlags)) { in getImmFixupKind()
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DX86BaseInfo.h565 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
566 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
569 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
570 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
575 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
576 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
591 inline unsigned isImmPCRel(uint64_t TSFlags) { in isImmPCRel() argument
592 switch (TSFlags & X86II::ImmMask) { in isImmPCRel()
609 inline unsigned isImmSigned(uint64_t TSFlags) { in isImmSigned() argument
610 switch (TSFlags & X86II::ImmMask) { in isImmSigned()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonInstPrinter.cpp34 static int getMinValue(uint64_t TSFlags) { in getMinValue() argument
36 (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask; in getMinValue()
38 (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask; in getMinValue()
48 static int getMaxValue(uint64_t TSFlags) { in getMaxValue() argument
50 (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask; in getMaxValue()
52 (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask; in getMaxValue()
61 static bool isExtended(uint64_t TSFlags) { in isExtended() argument
62 return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask; in isExtended()
66 static bool isExtendable(uint64_t TSFlags) LLVM_ATTRIBUTE_UNUSED;
68 static bool isExtendable(uint64_t TSFlags) { in isExtendable() argument
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DHexagonMCInstrInfo.cpp25 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getBitCount()
32 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getCExtOpNum()
51 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMaxValue()
66 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMinValue()
80 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValue()
94 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getType()
102 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
154 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtendable()
161 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtended()
168 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isNewValue()
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/external/llvm/lib/Target/NVPTX/
DNVPTXInstrFormats.td50 let TSFlags{3-0} = VecInstType;
51 let TSFlags{4-4} = IsSimpleMove;
52 let TSFlags{5-5} = IsLoad;
53 let TSFlags{6-6} = IsStore;
54 let TSFlags{7} = IsTex;
55 let TSFlags{9-8} = IsSuld;
56 let TSFlags{10} = IsSust;
57 let TSFlags{11} = IsSurfTexQuery;
58 let TSFlags{12} = IsTexModeUnified;
DNVPTXInstrInfo.cpp71 unsigned TSFlags = in isMoveInstr() local
72 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift; in isMoveInstr()
73 isMove = (TSFlags == 1); in isMoveInstr()
113 unsigned TSFlags = in isLoadInstr() local
114 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift; in isLoadInstr()
115 isLoad = (TSFlags == 1); in isLoadInstr()
124 unsigned TSFlags = in isStoreInstr() local
125 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift; in isStoreInstr()
126 isStore = (TSFlags == 1); in isStoreInstr()
DNVPTXReplaceImageHandles.cpp83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { in processInstr()
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { in processInstr()
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { in processInstr()
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); in processInstr()
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { in processInstr()
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) { in processInstr()
/external/llvm/lib/Target/R600/
DSIInstrInfo.h143 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
147 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
151 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
155 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
159 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
163 return get(Opcode).TSFlags & SIInstrFlags::SOPK; in isSOPK()
167 return get(Opcode).TSFlags & SIInstrFlags::SOPP; in isSOPP()
171 return get(Opcode).TSFlags & SIInstrFlags::VOP1; in isVOP1()
175 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
179 return get(Opcode).TSFlags & SIInstrFlags::VOP3; in isVOP3()
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DSIInstrFormats.td44 let TSFlags{0} = VM_CNT;
45 let TSFlags{1} = EXP_CNT;
46 let TSFlags{2} = LGKM_CNT;
48 let TSFlags{3} = SALU;
49 let TSFlags{4} = VALU;
51 let TSFlags{5} = SOP1;
52 let TSFlags{6} = SOP2;
53 let TSFlags{7} = SOPC;
54 let TSFlags{8} = SOPK;
55 let TSFlags{9} = SOPP;
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DR600InstrFormats.td44 let TSFlags{4} = Trig;
45 let TSFlags{5} = Op3;
49 let TSFlags{6} = isVector;
50 let TSFlags{8-7} = FlagOperandIdx;
51 let TSFlags{9} = HasNativeOperands;
52 let TSFlags{10} = Op1;
53 let TSFlags{11} = Op2;
54 let TSFlags{12} = VTXInst;
55 let TSFlags{13} = TEXInst;
56 let TSFlags{14} = ALUInst;
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DSIInsertWaits.cpp142 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags; in getHwCounts() local
145 Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT); in getHwCounts()
148 Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT && in getHwCounts()
152 if (TSFlags & SIInstrFlags::LGKM_CNT) { in getHwCounts()
DR600Defines.h62 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
63 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
DR600InstrInfo.cpp39 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG; in isTrig()
43 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; in isVector()
132 unsigned TargetFlags = get(Opcode).TSFlags; in isALUInstr()
138 unsigned TargetFlags = get(Opcode).TSFlags; in hasInstrModifiers()
146 unsigned TargetFlags = get(Opcode).TSFlags; in isLDSInstr()
198 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT); in isExport()
1345 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0; in hasFlagOperand()
1350 unsigned TargetFlags = get(MI->getOpcode()).TSFlags; in getFlagOp()
1405 unsigned TargetFlags = get(MI->getOpcode()).TSFlags; in addFlag()
1426 unsigned TargetFlags = get(MI->getOpcode()).TSFlags; in clearFlag()
DR600OptimizeVectorRegisters.cpp134 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) in canSwizzle()
250 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) in SwizzleInput()
330 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) { in runOnMachineFunction()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormatsV4.td66 let TSFlags{4-0} = Type.Value;
70 let TSFlags{6} = isPredicated;
72 let TSFlags{7} = isPredicatedFalse;
74 let TSFlags{8} = isPredicatedNew;
78 let TSFlags{9} = isNewValue; // New-value consumer insn.
80 let TSFlags{10} = hasNewValue; // New-value producer insn.
82 let TSFlags{13-11} = opNewValue; // New-value produced operand.
84 let TSFlags{14} = isNVStorable; // Store that can become new-value store.
86 let TSFlags{15} = isNVStore; // New-value store insn.
90 let TSFlags{16} = isExtendable; // Insn may be extended.
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DHexagonInstrFormats.td100 let TSFlags{4-0} = Type.Value;
104 let TSFlags{5} = isSolo;
107 let TSFlags{6} = isSoloAX;
110 let TSFlags{7} = isSoloAin1;
114 let TSFlags{8} = isPredicated;
116 let TSFlags{9} = isPredicatedFalse;
118 let TSFlags{10} = isPredicatedNew;
120 let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
124 let TSFlags{12} = isNewValue; // New-value consumer insn.
126 let TSFlags{13} = hasNewValue; // New-value producer insn.
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DHexagonInstrInfo.cpp680 const uint64_t F = MID.TSFlags; in isExtendable()
701 const uint64_t F = MI->getDesc().TSFlags; in isExtended()
837 const uint64_t F = MI->getDesc().TSFlags; in isNewValueStore()
843 const uint64_t F = get(Opcode).TSFlags; in isNewValueStore()
1054 const uint64_t F = MI->getDesc().TSFlags; in isPredicated()
1060 const uint64_t F = get(Opcode).TSFlags; in isPredicated()
1066 const uint64_t F = MI->getDesc().TSFlags; in isPredicatedTrue()
1074 const uint64_t F = get(Opcode).TSFlags; in isPredicatedTrue()
1083 const uint64_t F = MI->getDesc().TSFlags; in isPredicatedNew()
1090 const uint64_t F = get(Opcode).TSFlags; in isPredicatedNew()
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/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
56 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { in getHazardType()
/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp287 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
289 isFirst = TSFlags & PPCII::PPC970_First; in GetInstrType()
290 isSingle = TSFlags & PPCII::PPC970_Single; in GetInstrType()
291 isCracked = TSFlags & PPCII::PPC970_Cracked; in GetInstrType()
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); in GetInstrType()
/external/llvm/lib/Target/R600/MCTargetDesc/
DR600MCCodeEmitter.cpp136 ((Desc.TSFlags & R600_InstFlag::OP1) || in EncodeInstruction()
137 Desc.TSFlags & R600_InstFlag::OP2)) { in EncodeInstruction()
175 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/external/llvm/lib/Target/X86/
DX86InstrFormats.td304 // TSFlags layout should be kept in sync with X86BaseInfo.h.
305 let TSFlags{6-0} = FormBits;
306 let TSFlags{8-7} = OpSizeBits;
307 let TSFlags{10-9} = AdSizeBits;
308 let TSFlags{13-11} = OpPrefixBits;
309 let TSFlags{16-14} = OpMapBits;
310 let TSFlags{17} = hasREX_WPrefix;
311 let TSFlags{21-18} = ImmT.Value;
312 let TSFlags{24-22} = FPForm.Value;
313 let TSFlags{25} = hasLockPrefix;
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/external/llvm/lib/Target/X86/InstPrinter/
DX86IntelInstPrinter.cpp39 uint64_t TSFlags = Desc.TSFlags; in printInst() local
41 if (TSFlags & X86II::LOCK) in printInst()
DX86ATTInstPrinter.cpp43 uint64_t TSFlags = Desc.TSFlags; in printInst() local
50 if (TSFlags & X86II::LOCK) in printInst()
/external/mesa3d/src/gallium/drivers/radeon/
DR600InstrInfo.cpp40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG; in isTrig()
45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; in isVector()
485 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0; in hasFlagOperand()
490 unsigned FlagIndex = GET_FLAG_OPERAND_IDX(get(MI->getOpcode()).TSFlags); in getFlagOp()
DAMDGPUInstructions.td25 let TSFlags{42-40} = Gen;
26 let TSFlags{63-48} = AMDILOp;

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