| /external/llvm/lib/CodeGen/ |
| D | IntrinsicLowering.cpp | 184 Value *Tmp4 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
198 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1"); in LowerBSWAP()
200 V = Builder.CreateOr(Tmp4, Tmp2, "bswap.i32"); in LowerBSWAP()
212 Value* Tmp4 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
235 Tmp4 = Builder.CreateAnd(Tmp4, in LowerBSWAP()
249 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3"); in LowerBSWAP()
252 Tmp4 = Builder.CreateOr(Tmp4, Tmp2, "bswap.or6"); in LowerBSWAP()
253 V = Builder.CreateOr(Tmp8, Tmp4, "bswap.i64"); in LowerBSWAP()
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| /external/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 139 Value *Tmp4 = Builder.CreateXor(Q_Mag, Q_Sgn); in generateSignedDivisionCode() local
140 Value *Q = Builder.CreateSub(Tmp4, Q_Sgn); in generateSignedDivisionCode()
284 Value *Tmp4 = Builder.CreateAdd(Divisor, NegOne); in generateUnsignedDivisionCode() local
315 Value *Tmp9 = Builder.CreateSub(Tmp4, Tmp7); in generateUnsignedDivisionCode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2694 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in ExpandBSWAP() local
2702 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); in ExpandBSWAP()
2708 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); in ExpandBSWAP()
2710 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); in ExpandBSWAP()
2716 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2723 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); in ExpandBSWAP()
2728 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); in ExpandBSWAP()
2731 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); in ExpandBSWAP()
2732 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); in ExpandBSWAP()
2843 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in ExpandNode() local
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2342 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2343 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2346 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2357 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
2486 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2487 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2494 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; in Select() local
2495 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in Select()
2496 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; in Select()
2548 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
|
| /external/clang/lib/CodeGen/ |
| D | CGExprComplex.cpp | 777 llvm::Value *Tmp4 = Builder.CreateMul(RHSr, RHSr); // c*c in EmitBinDiv() local
779 llvm::Value *Tmp6 = Builder.CreateAdd(Tmp4, Tmp5); // cc+dd in EmitBinDiv()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1120 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]); in LowerLOAD() local
1123 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2); in LowerLOAD()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 6393 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS() local
6397 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); in LowerSHL_PARTS()
6422 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS() local
6426 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); in LowerSRL_PARTS()
6450 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS() local
6456 Tmp4, Tmp6, ISD::SETLE); in LowerSRA_PARTS()
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