| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in AMDGPUTargetLowering()
96 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 SDIVREM, UDIVREM, enumerator
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| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 877 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults() local
879 Results.push_back(UDIVREM); in ReplaceNodeResults()
886 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults() local
888 Results.push_back(UDIVREM.getValue(1)); in ReplaceNodeResults()
916 case ISD::UDIVREM: { in ReplaceNodeResults()
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| D | AMDGPUISelLowering.cpp | 271 setOperationAction(ISD::UDIVREM, VT, Custom); in AMDGPUTargetLowering()
337 setOperationAction(ISD::UDIVREM, VT, Custom); in AMDGPUTargetLowering()
609 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
1664 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
1878 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); in LowerSDIVREM()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 177 case ISD::UDIVREM: return "udivrem"; in getOperationName()
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| D | LegalizeDAG.cpp | 2211 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in useDivRem()
3500 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3531 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3566 case ISD::UDIVREM: in ExpandNode()
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| D | DAGCombiner.cpp | 1323 case ISD::UDIVREM: return visitUDIVREM(N); in visit()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 130 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
137 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
167 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
214 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
371 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, in LowerOperation()
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| D | MipsISelLowering.cpp | 406 setTargetDAGCombine(ISD::UDIVREM); in MipsTargetLowering()
796 case ISD::UDIVREM: in PerformDAGCombine()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 155 setOperationAction(ISD::UDIVREM, MVT::i8, Expand); in MSP430TargetLowering()
161 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 117 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in BPFTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1305 setOperationAction(ISD::UDIVREM, VT, Expand); in HexagonTargetLowering()
1639 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in HexagonTargetLowering()
1642 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1410 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1417 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 156 setOperationAction(ISD::UDIVREM, VT, Custom); in SystemZTargetLowering()
2728 case ISD::UDIVREM: in LowerOperation()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 353 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2437 case ISD::UDIVREM: in Select()
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| D | X86ISelLowering.cpp | 707 setOperationAction(ISD::UDIVREM, VT, Expand); in X86TargetLowering()
1527 setOperationAction(ISD::UDIVREM, MVT::i128, Custom); in X86TargetLowering()
15970 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break; in LowerWin64_i128OP()
17306 case ISD::UDIVREM: { in ReplaceNodeResults()
23362 if (N0.getOpcode() == ISD::UDIVREM && in PerformZExtCombine()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 738 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in ARMTargetLowering()
741 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in ARMTargetLowering()
6329 case ISD::UDIVREM: return LowerDivRem(Op, DAG); in LowerOperation()
10753 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in PPCTargetLowering()
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in PPCTargetLowering()
467 setOperationAction(ISD::UDIVREM, VT, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 256 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in AArch64TargetLowering()
257 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in AArch64TargetLowering()
|