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Searched refs:UMLAL (Results 1 – 16 of 16) sorted by relevance

/external/llvm/test/MC/ARM/
Dmul-v4.s1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
Dbasic-thumb2-instructions.s3341 @ UMLAL
Dbasic-arm-instructions.s3284 @ UMLAL
/external/llvm/lib/Target/ARM/
DARMISelLowering.h165 UMLAL, // 64bit Unsigned Accumulate Multiply enumerator
DARMInstrInfo.td93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
3880 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3910 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
5657 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5671 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
DARMISelDAGToDAG.cpp2657 case ARMISD::UMLAL:{ in Select()
2669 ARM::UMLAL : ARM::UMLALv5, in Select()
DARMScheduleSwift.td1328 (instregex "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT",
DARMScheduleA9.td2501 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
DARMISelLowering.cpp1107 case ARMISD::UMLAL: return "ARMISD::UMLAL"; in getTargetNodeName()
7929 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL()
/external/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td522 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
DAArch64InstrInfo.td3280 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3306 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
4364 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
/external/vixl/doc/
Dsupported-instructions.md4188 ### UMLAL ### subsection
4198 ### UMLAL ### subsection
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt2288 # UMLAL
Dthumb2.txt2428 # UMLAL
/external/valgrind/none/tests/arm/
Dv6intARM.stdout.exp555 UMLAL
Dv6media.stdout.exp36 UMLAL