Searched refs:UNINDEXED (Results 1 – 16 of 16) sorted by relevance
737 UNINDEXED = 0, enumerator
1851 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }1854 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }2091 Ld->getAddressingMode() == ISD::UNINDEXED;2121 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;2129 St->getAddressingMode() == ISD::UNINDEXED;2145 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
462 if (AM != ISD::UNINDEXED) { in SelectLoad()553 if (AM != ISD::UNINDEXED) { in SelectStore()593 LD->getAddressingMode() != ISD::UNINDEXED) { in SelectMul()619 LD->getAddressingMode() != ISD::UNINDEXED) { in SelectMul()
4802 bool Indexed = AM != ISD::UNINDEXED; in getLoad()4837 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()4846 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()4857 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()4867 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()4921 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile(), in getStore()4931 ISD::UNINDEXED, false, VT, MMO); in getStore()4990 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile(), in getTruncStore()5000 ISD::UNINDEXED, true, SVT, MMO); in getTruncStore()5043 ID.AddInteger(encodeMemSDNodeFlags(ExtTy, ISD::UNINDEXED, in getMaskedLoad()[all …]
219 SDValue Result = DAG.getLoad(ISD::UNINDEXED, in ScalarizeVecRes_LOAD()964 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()971 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
293 assert(ST->getAddressingMode() == ISD::UNINDEXED && in ExpandUnalignedStore()417 assert(LD->getAddressingMode() == ISD::UNINDEXED && in ExpandUnalignedLoad()
8634 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPreIndexedLoadStore()8859 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPostIndexedLoadStore()8941 assert(AM != ISD::UNINDEXED); in SplitIndexingFromLoad()
656 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;766 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
516 ST->getAddressingMode() == ISD::UNINDEXED &&
422 LD->getAddressingMode() != ISD::UNINDEXED || in isCalleeLoad()
1445 if (AM == ISD::UNINDEXED) in SelectARMIndexedLoad()1518 if (AM == ISD::UNINDEXED) in SelectT2IndexedLoad()
391 return DAG.getLoad(ISD::UNINDEXED, Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, in LowerParameter()
1705 SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
2355 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, in performStoreCombine()
1251 ST->getAddressingMode() == ISD::UNINDEXED;
META-INF/MANIFEST.MF META-INF/ECLIPSEF.SF META-INF/ECLIPSEF ...