| /external/llvm/test/CodeGen/ARM/ |
| D | vfcmp.ll | 17 ; olt is implemented with VCGT
39 ; uge is implemented with VCGT/VMVN
51 ; ule is implemented with VCGT/VMVN
87 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
101 ; one is implemented with VCGT/VCGT/VORR
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
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| D | vicmp.ll | 6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
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| /external/libhevc/common/arm/ |
| D | ihevc_sao_edge_offset_class1.s | 132 VCGT.U8 Q6,Q5,Q4 @vcgtq_u8(pu1_cur_row, pu1_top_row)
147 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
162 VCGT.U8 Q11,Q9,Q15 @II vcgtq_u8(pu1_cur_row, pu1_top_row)
226 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
277 VCGT.U8 Q6,Q5,Q4 @vcgtq_u8(pu1_cur_row, pu1_top_row)
289 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row)
301 VCGT.U8 Q11,Q9,Q15 @II vcgtq_u8(pu1_cur_row, pu1_next_row)
345 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row)
346 VCGT.U8 Q7,Q9,Q5 @vcltq_u8(pu1_cur_row, pu1_next_row)
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| D | ihevc_sao_edge_offset_class1_chroma.s | 137 VCGT.U8 Q6,Q5,Q14 @vcgtq_u8(pu1_cur_row, pu1_top_row)
152 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
167 VCGT.U8 Q11,Q9,Q15 @II vcgtq_u8(pu1_cur_row, pu1_top_row)
239 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
295 VCGT.U8 Q6,Q5,Q14 @vcgtq_u8(pu1_cur_row, pu1_top_row)
307 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row)
319 VCGT.U8 Q11,Q9,Q15 @II vcgtq_u8(pu1_cur_row, pu1_next_row)
376 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row)
377 VCGT.U8 Q7,Q9,Q5 @vcltq_u8(pu1_cur_row, pu1_next_row)
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| D | ihevc_sao_edge_offset_class0_chroma.s | 163 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
177 VCGT.U8 Q13,Q15,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
191 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
206 VCGT.U8 Q13,Q15,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
326 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
340 VCGT.U8 Q13,Q15,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
351 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
369 VCGT.U8 Q13,Q15,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
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| D | ihevc_sao_edge_offset_class0.s | 157 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
174 VCGT.U8 Q15,Q13,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
185 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
203 VCGT.U8 Q15,Q13,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
297 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
305 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
|
| D | ihevc_sao_edge_offset_class2.s | 248 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
293 VCGT.U8 Q5,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
360 VCGT.U8 Q12,Q6,Q11 @II vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
375 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
461 VCGT.U8 Q5,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
560 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
607 VCGT.U8 Q10,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
688 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
738 VCGT.U8 Q10,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
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| D | ihevc_sao_edge_offset_class3.s | 263 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
308 VCGT.U8 Q5,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
385 VCGT.U8 Q12,Q6,Q9 @II vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
410 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
499 VCGT.U8 Q12,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
601 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
648 VCGT.U8 Q10,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
739 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
786 VCGT.U8 Q10,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
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| D | ihevc_sao_edge_offset_class2_chroma.s | 340 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
402 VCGT.U8 Q10,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
476 VCGT.U8 Q11,Q6,Q14 @II vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
527 VCGT.U8 Q10,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
621 VCGT.U8 Q11,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
732 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
778 VCGT.U8 Q11,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
877 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
922 VCGT.U8 Q11,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
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| D | ihevc_sao_edge_offset_class3_chroma.s | 330 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
394 VCGT.U8 Q10,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
477 VCGT.U8 Q11,Q6,Q14 @II vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
517 VCGT.U8 Q11,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
628 VCGT.U8 Q10,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
722 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
800 VCGT.U8 Q11,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
903 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
970 VCGT.U8 Q11,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 101 VCGT, // Vector compare greater than. enumerator
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| D | ARMISelLowering.cpp | 1068 case ARMISD::VCGT: return "ARMISD::VCGT"; in getTargetNodeName()
4370 case ISD::SETGT: Opc = ARMISD::VCGT; break; in LowerVSETCC()
4376 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; in LowerVSETCC()
4385 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); in LowerVSETCC()
4386 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC()
4394 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); in LowerVSETCC()
4405 case ISD::SETGT: Opc = ARMISD::VCGT; break; in LowerVSETCC()
4447 else if (Opc == ARMISD::VCGT) in LowerVSETCC()
4461 case ARMISD::VCGT: in LowerVSETCC()
|
| D | ARMScheduleSwift.td | 1585 "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
|
| D | ARMScheduleA9.td | 2411 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
|
| D | ARMInstrNEON.td | 501 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
4666 // VCGT : Vector Compare Greater Than
7686 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7718 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 539 def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
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| /external/valgrind/none/tests/arm/ |
| D | neon128.stdout.exp | 345 ---- VCGT ----
1825 ---- VCGT #0 ----
3804 ---- VCGT (fp) ----
4075 ---- VCGT (fp) #0 ----
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| D | neon64.stdout.exp | 452 ---- VCGT ----
3069 ---- VCGT #0 ----
5689 ---- VCGT (fp) ----
6205 ---- VCGT (fp) #0 ----
|