| /external/llvm/test/Transforms/LoopVectorize/AArch64/ |
| D | arbitrary-induction-step.ll | 2 …-vectorize -force-vector-interleave=1 -force-vector-width=2 | FileCheck %s --check-prefix=FORCE-VEC
23 ; FORCE-VEC-LABEL: @ind_plus2(
24 ; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>*
25 ; FORCE-VEC: mul nsw <2 x i32>
26 ; FORCE-VEC: add nsw <2 x i32>
27 ; FORCE-VEC: %index.next = add i64 %index, 2
28 ; FORCE-VEC: icmp eq i64 %index.next, 512
67 ; FORCE-VEC-LABEL: @ind_minus2(
68 ; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>*
69 ; FORCE-VEC: mul nsw <2 x i32>
[all …]
|
| /external/llvm/test/Transforms/LoopVectorize/ |
| D | if-pred-stores.ll | 2 …-vector-interleave=1 -loop-vectorize -enable-cond-stores-vec < %s | FileCheck %s --check-prefix=VEC
11 ; VEC-LABEL: test
12 ; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100>
13 ; VEC: %[[v9:.+]] = add nsw <2 x i32> %{{.*}}, <i32 20, i32 20>
14 ; VEC: %[[v10:.+]] = and <2 x i1> %[[v8]], <i1 true, i1 true>
15 ; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[v10]], i32 0
16 ; VEC: %[[v12:.+]] = icmp eq i1 %[[v11]], true
17 ; VEC: br i1 %[[v12]], label %[[cond:.+]], label %[[else:.+]]
19 ; VEC: [[cond]]:
20 ; VEC: %[[v13:.+]] = extractelement <2 x i32> %[[v9]], i32 0
[all …]
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | sincospi.ll | 1 …stcombine -S < %s -mtriple=x86_64-apple-macosx10.9 | FileCheck %s --check-prefix=CHECK-FLOAT-IN-VEC
26 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load float, float* @var32
27 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float [[VAL]])
28 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
29 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
45 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float 1.000000e+0…
46 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
47 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
63 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load double, double* @var64
64 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VA…
[all …]
|
| /external/mesa3d/src/gallium/drivers/nv30/ |
| D | nvfx_vertprog.c | 495 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, in nvfx_vertprog_parse_instruction()
506 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, in nvfx_vertprog_parse_instruction()
517 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, in nvfx_vertprog_parse_instruction()
552 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, abs(src[0]), none, none)); in nvfx_vertprog_parse_instruction()
555 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1])); in nvfx_vertprog_parse_instruction()
558 nvfx_vp_emit(vpc, arith(0, VEC, ARL, dst, mask, src[0], none, none)); in nvfx_vertprog_parse_instruction()
562 nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, neg(src[0]), none, none)); in nvfx_vertprog_parse_instruction()
563 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none)); in nvfx_vertprog_parse_instruction()
566 insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none); in nvfx_vertprog_parse_instruction()
570 insn = arith(sat, VEC, MOV, dst, mask, src[2], none, none); in nvfx_vertprog_parse_instruction()
[all …]
|
| /external/llvm/unittests/Transforms/Utils/ |
| D | ASanStackFrameLayoutTest.cpp | 42 #define VEC(a) \ in TEST() macro
88 TestLayout(VEC(t), 8, 32, in TEST()
95 TestLayout(VEC(t), 8, 32, in TEST()
100 #undef VEC in TEST()
|
| /external/antlr/antlr-3.4/runtime/CSharp3/Sources/Antlr3.Runtime.Test/Composition/ |
| D | VecMath_Parser.g3 | 9 VEC;
32 | OPEN_SQUARE expr ( COMMA expr )* CLOSE_SQUARE -> ^( VEC expr+ )
|
| D | Simplify.g3 | 20 : ^( MULT INT ^(VEC (e+=.)+) ) -> ^(VEC ^(MULT INT $e)+)
|
| /external/valgrind/ |
| D | README.aarch64 | 223 LDP,STP (immediate, simm7) (FP&VEC)
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | vec.ll | 1 ; Test the MSA intrinsics that are encoded with the VEC instruction format.
|
| /external/clang/lib/Frontend/Rewrite/ |
| D | RewriteModernObjC.cpp | 3958 #define SKIP_BITFIELDS(IX, ENDIX, VEC) { \ argument
3959 while ((IX < ENDIX) && VEC[IX]->isBitField()) \
|