Searched refs:VGPR (Results 1 – 17 of 17) sorted by relevance
| /external/llvm/lib/Target/R600/ |
| D | SIRegisterInfo.td | 57 // VGPR registers
59 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
115 // VGPR 32-bit registers
117 (add (sequence "VGPR%u", 0, 255))>;
119 // VGPR 64-bit registers
124 // VGPR 96-bit registers
130 // VGPR 128-bit registers
137 // VGPR 256-bit registers
148 // VGPR 512-bit registers
252 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
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| D | SIMachineFunctionInfo.h | 37 unsigned VGPR; member
39 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } in SpilledReg()
40 SpilledReg() : VGPR(0), Lane(-1) { } in SpilledReg()
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| D | SIIntrinsics.td | 27 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
29 llvm_i32_ty, // vaddr(VGPR)
43 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
45 llvm_anyint_ty, // vaddr(VGPR)
59 [llvm_v4f32_ty], // vdata(VGPR)
60 [llvm_anyint_ty, // vaddr(VGPR)
75 [llvm_v4f32_ty], // vdata(VGPR)
76 [llvm_anyint_ty, // vaddr(VGPR)
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| D | SIRegisterInfo.cpp | 221 if (Spill.VGPR == AMDGPU::NoRegister) { in eliminateFrameIndex()
228 Spill.VGPR) in eliminateFrameIndex()
252 if (Spill.VGPR == AMDGPU::NoRegister) { in eliminateFrameIndex()
263 .addReg(Spill.VGPR) in eliminateFrameIndex()
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| D | SIMachineFunctionInfo.cpp | 66 Spill.VGPR = LaneVGPRs[LaneVGPRIdx]; in getSpilledReg()
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| D | SIInstrInfo.td | 94 SDTCisVT<1, iAny>, // vdata(VGPR)
96 SDTCisVT<3, i32>, // vaddr(VGPR)
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| D | SIInstructions.td | 2793 // Offset in an 32Bit VGPR
2895 // needs to be a VGPR. The SGPR copy pass will fix this, and it's
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIGenRegisterInfo.pl | 134 my @VGPR;
137 $VGPR[$i] = "VGPR$i";
221 for (my $i = 0; $i <= $#VGPR; $i++) {
222 push (@{$hw_values{$i}}, $VGPR[$i]);
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| /external/clang/test/SemaOpenCL/ |
| D | amdgpu-num-register-attrs.cl | 20 // Check 0 VGPR is accepted.
26 // Check both 0 SGPR and VGPR is accepted.
29 // Too large VGPR value.
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| /external/llvm/test/CodeGen/R600/ |
| D | address-space.ll | 8 ; FIXME: Extra V_MOV from SGPR to VGPR for second read. The address is
9 ; already in a VGPR after the first read.
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| D | add_i64.ll | 20 ; Check that the SGPR add operand is correctly moved to a VGPR.
31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
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| D | sgpr-copy-duplicate-operand.ll | 4 ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
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| D | add.ll | 132 ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
133 ; to a VGPR before doing the add.
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| D | si-lod-bias.ll | 4 ; This shader has the potential to generated illegal VGPR to SGPR copies if
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| D | salu-to-valu.ll | 15 ; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
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| D | local-atomics.ll | 31 ; XXX - Is it really necessary to load 4 into VGPR?
327 ; XXX - Is it really necessary to load 4 into VGPR?
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| D | sgpr-copy.ll | 4 ; This test checks that no VGPR to SGPR copies are created by the register
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