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Searched refs:VLD (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64Schedule.td95 // Read the unwritten lanes of the VLD's destination registers.
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td1013 // VLD/VST instructions and checking the alignment is not specified.
1024 // VLD/VST instructions and checking the alignment value.
1035 // VLD/VST instructions and checking the alignment value.
1046 // VLD/VST instructions and checking the alignment value.
1057 // for VLD/VST instructions and checking the alignment value.
1068 // encoding for VLD/VST instructions and checking the alignment value.
1078 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1099 // VLD-dup instruction and checking the alignment is not specified.
1109 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1120 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
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DARMISelLowering.cpp8976 SDNode *VLD = N->getOperand(0).getNode(); in CombineVLDDUP() local
8977 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) in CombineVLDDUP()
8981 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); in CombineVLDDUP()
8998 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); in CombineVLDDUP()
8999 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
9017 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; in CombineVLDDUP()
9018 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); in CombineVLDDUP()
9019 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, in CombineVLDDUP()
9024 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
9040 DCI.CombineTo(VLD, VLDDupResults); in CombineVLDDUP()
DARMInstrNEON.td627 // Classes for VLD* pseudo-instructions with multi-register operands.
1028 // Classes for VLD*LN pseudo-instructions with multi-register operands.