Searched refs:VMOVRRD (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMHazardRecognizer.cpp | 27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
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| D | MLxExpansionPass.cpp | 192 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
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| D | ARMISelLowering.h | 77 VMOVRRD, // double to two gprs. enumerator
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| D | ARMISelLowering.cpp | 1044 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName()
1435 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
2222 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2244 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2299 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly()
3434 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
3436 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
3926 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
3942 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4037 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
[all …]
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| D | ARMISelDAGToDAG.cpp | 434 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
2621 case ARMISD::VMOVRRD: in Select()
2622 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, in Select()
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| D | ARMInstrVFP.td | 846 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
1855 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
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| D | ARMFastISel.cpp | 1999 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
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| D | ARMBaseInstrInfo.cpp | 4565 case ARM::VMOVRRD: in getExtractSubregLikeInputs()
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| /external/llvm/test/CodeGen/ARM/ |
| D | vector-DAGCombine.ll | 38 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
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