Searched refs:VOP1 (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/docs/ |
| D | R600Usage.rst | 73 VOP1, VOP2, VOP3, VOPC Instructions
79 VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
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| /external/llvm/lib/Target/R600/ |
| D | CIInstructions.td | 19 // VOP1 Instructions
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| D | SIDefines.h | 28 VOP1 = 1 << 10, enumerator
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| D | SIInstrFormats.td | 30 field bits<1> VOP1 = 0;
57 let TSFlags{10} = VOP1;
112 let VOP1 = 1;
572 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
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| D | SIInstrInfo.h | 171 return get(Opcode).TSFlags & SIInstrFlags::VOP1; in isVOP1()
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| D | SIInstrInfo.td | 800 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
839 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
852 // VOP1 with modifiers
856 // VOP1 without modifiers
1013 VOP1<op.SI, outs, ins, asm, []>,
1017 VOP1<op.VI, outs, ins, asm, []>,
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| D | SIInstructions.td | 1230 // VOP1 Instructions
1245 def V_READFIRSTLANE_B32 : VOP1 <
2227 // VOP1 Patterns
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 49 VOP1 = 12, enumerator
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIInstrInfo.td | 369 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
380 let EncodingType = 12; // SIInstrEncodingType::VOP1
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| D | SIInstrFormats.td | 49 VOP1 <
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| D | SIInstructions.td | 886 class V_MOV_IMM <Operand immType, SDNode immNode> : VOP1 <
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