Searched refs:VREV16 (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 154 VREV16, // reverse elements within 16-bit halfwords enumerator
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| D | ARMScheduleSwift.td | 1579 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
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| D | ARMISelLowering.cpp | 1099 case ARMISD::VREV16: return "ARMISD::VREV16"; in getTargetNodeName()
4185 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1); in getCTPOP16BitCounts()
5418 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
5542 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); in LowerVECTOR_SHUFFLE()
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| D | ARMInstrNEON.td | 576 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
5982 // VREV16 : Vector Reverse elements within 16-bit halfwords
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 758 def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>;
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