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Searched refs:_3DSTATE_PIPE_CONTROL (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_batchbuffer.c383 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
390 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
397 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
418 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in gen7_emit_vs_workaround_flush()
470 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_post_sync_nonzero_flush()
478 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_post_sync_nonzero_flush()
517 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_batchbuffer_emit_mi_flush()
531 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | in intel_batchbuffer_emit_mi_flush()
Dbrw_queryobj.c62 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in write_timestamp()
70 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2)); in write_timestamp()
81 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | in write_timestamp()
102 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2)); in write_depth_count()
114 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | in write_depth_count()
Dgen6_vs_state.c219 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in upload_vs_state()
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_batchbuffer.c383 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
390 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
397 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
418 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in gen7_emit_vs_workaround_flush()
470 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_post_sync_nonzero_flush()
478 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_post_sync_nonzero_flush()
517 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_batchbuffer_emit_mi_flush()
531 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | in intel_batchbuffer_emit_mi_flush()
/external/mesa3d/src/mesa/drivers/dri/intel/
Dintel_batchbuffer.c383 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
390 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
397 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
418 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in gen7_emit_vs_workaround_flush()
470 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_post_sync_nonzero_flush()
478 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_post_sync_nonzero_flush()
517 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_batchbuffer_emit_mi_flush()
531 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | in intel_batchbuffer_emit_mi_flush()
Dintel_reg.h61 #define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24)) macro