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Searched refs:addRegMask (Results 1 – 10 of 10) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h153 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const { in addRegMask() function
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp393 MIB.addRegMask(RM->getRegMask()); in AddOperand()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp1170 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in fastLowerCall()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp2268 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in ARMEmitLibcall()
2419 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in SelectCall()
DARMISelLowering.cpp6590 MIB.addRegMask(RI.getNoPreservedMask()); in EmitSjLjDispatchBlock()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1552 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in fastLowerCall()
DPPCISelLowering.cpp8150 MIB.addRegMask(TRI->getNoPreservedMask()); in emitEHSjLjSetJmp()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp3108 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in fastLowerCall()
DX86ISelLowering.cpp18671 .addRegMask(RegMask) in EmitLoweredSegAlloca()
18679 .addRegMask(RegMask) in EmitLoweredSegAlloca()
18688 .addRegMask(RegMask) in EmitLoweredSegAlloca()
18761 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
18772 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
18783 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
18903 MIB.addRegMask(RegInfo->getNoPreservedMask()); in emitEHSjLjSetJmp()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp3167 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in fastLowerCall()