| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vecFold.ll | 53 …%vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) noun…
54 …%vaddhn2.i10 = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) no…
55 ; CHECK: addhn.4h v0, v0, v1
67 …%vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) noun…
70 ; CHECK: addhn.4h v0, v0, v1
126 …%vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) noun…
141 declare <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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| D | arm64-vadd.ll | 5 ;CHECK: addhn.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
14 ;CHECK: addhn.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
23 ;CHECK: addhn.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
32 ;CHECK: addhn.8b
34 %vaddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
35 …%vaddhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %a, <8 x i16> %b) nou…
42 ;CHECK: addhn.4h
[all …]
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| D | arm64-neon-3vdiff.ll | 547 ; CHECK: addhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
557 ; CHECK: addhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
567 ; CHECK: addhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
577 ; CHECK: addhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
587 ; CHECK: addhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
597 ; CHECK: addhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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| /external/llvm/test/MC/AArch64/ |
| D | neon-3vdiff.s | 369 addhn v0.8b, v1.8h, v2.8h
370 addhn v0.4h, v1.4s, v2.4s
371 addhn v0.2s, v1.2d, v2.2d
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| D | arm64-advsimd.s | 39 addhn.8b v0, v0, v0
41 addhn.4h v0, v0, v0
43 addhn.2s v0, v0, v0
46 ; CHECK: addhn.8b v0, v0, v0 ; encoding: [0x00,0x40,0x20,0x0e]
48 ; CHECK: addhn.4h v0, v0, v0 ; encoding: [0x00,0x40,0x60,0x0e]
50 ; CHECK: addhn.2s v0, v0, v0 ; encoding: [0x00,0x40,0xa0,0x0e]
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| D | neon-diagnostics.s | 2763 addhn v0.8b, v1.8h, v2.8d
2764 addhn v0.4h, v1.4s, v2.4h
2765 addhn v0.2s, v1.2d, v2.2s
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 44 # CHECK: addhn.8b v0, v0, v0
46 # CHECK: addhn.4h v0, v0, v0
48 # CHECK: addhn.2s v0, v0, v0
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| D | neon-instructions.txt | 1430 # CHECK: addhn v0.8b, v1.8h, v2.8h
1431 # CHECK: addhn v0.4h, v1.4s, v2.4s
1432 # CHECK: addhn v0.2s, v1.2d, v2.2d
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.c | 2725 GEN_BINARY_TEST(addhn, 2s, 2d, 2d)
2727 GEN_BINARY_TEST(addhn, 4h, 4s, 4s)
2729 GEN_BINARY_TEST(addhn, 8b, 8h, 8h)
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| D | fp_and_simd.stdout.exp | 26947 addhn v9.2s, v7.2d, v8.2d f17a5fa50e8c4ea360753ff4b3136416 8b4f68a2d06b77faad1aa7687bf0734a 0000…
26949 addhn v9.4h, v7.4s, v8.4s f4b97b2003b134783ff7bfea289b6d2d ca0e41c80df3d06fa23573265b5d8647 0000…
26951 addhn v9.8b, v7.8h, v8.8h 750d85ba4d0b5b78e0c7aa4ee70264af 1c112f0bd4fe302d310d1191fa368d0d 0000…
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| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 2263 V(addhn) \
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| D | macro-assembler-a64.h | 2083 V(addhn, Addhn) \
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| D | assembler-a64.h | 3476 void addhn(const VRegister& vd,
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| D | simulator-a64.cc | 2799 case NEON_ADDHN: addhn(vf, rd, rn, rm); break; in VisitNEON3Different()
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| D | logic-a64.cc | 3303 LogicVRegister Simulator::addhn(VectorFormat vform, in addhn() function in vixl::Simulator
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| D | assembler-a64.cc | 2410 V(addhn, NEON_ADDHN, vd.IsD()) \
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| /external/vixl/test/ |
| D | test-simulator-a64.cc | 3820 DEFINE_TEST_NEON_3DIFF_NARROW(addhn, Basic)
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| /external/vixl/doc/ |
| D | supported-instructions.md | 1423 void addhn(const VRegister& vd,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3244 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3337 // CodeGen patterns for addhn and subhn instructions, which can actually be
|