| /external/valgrind/VEX/priv/ |
| D | guest_tilegx_defs.h | 52 const VexArchInfo* archinfo,
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| D | guest_generic_bb_to_IR.h | 150 /*IN*/ const VexArchInfo* archinfo,
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| D | guest_arm64_defs.h | 51 const VexArchInfo* archinfo,
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| D | guest_ppc_defs.h | 62 const VexArchInfo* archinfo,
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| D | guest_arm_defs.h | 53 const VexArchInfo* archinfo,
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| D | guest_mips_defs.h | 52 const VexArchInfo* archinfo,
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| D | guest_s390_defs.h | 51 const VexArchInfo* archinfo,
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| D | guest_x86_defs.h | 61 const VexArchInfo* archinfo,
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| D | guest_amd64_defs.h | 61 const VexArchInfo* archinfo,
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| D | guest_mips_toIR.c | 12018 const VexArchInfo* archinfo, in disInstr_MIPS_WRK() argument
14468 if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM) { in disInstr_MIPS_WRK()
14517 if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) { in disInstr_MIPS_WRK()
14580 if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) { in disInstr_MIPS_WRK()
14642 if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) { in disInstr_MIPS_WRK()
14708 if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) { in disInstr_MIPS_WRK()
15307 if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM) { in disInstr_MIPS_WRK()
15314 if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) { in disInstr_MIPS_WRK()
15330 if (VEX_MIPS_PROC_DSP2(archinfo->hwcaps)) { in disInstr_MIPS_WRK()
15342 if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) { in disInstr_MIPS_WRK()
[all …]
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| D | guest_tilegx_toIR.c | 272 const VexArchInfo * archinfo, in disInstr_TILEGX_WRK() argument
2488 const VexArchInfo* archinfo, in disInstr_TILEGX() argument
2506 delta, archinfo, abiinfo, sigill_diag_IN); in disInstr_TILEGX()
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| D | guest_arm64_toIR.c | 6426 const VexArchInfo* archinfo) in dis_ARM64_branch_etc() argument
6709 vassert(archinfo->arm64_dMinLine_lg2_szB >= 2 in dis_ARM64_branch_etc()
6710 && archinfo->arm64_dMinLine_lg2_szB <= 17 in dis_ARM64_branch_etc()
6711 && archinfo->arm64_iMinLine_lg2_szB >= 2 in dis_ARM64_branch_etc()
6712 && archinfo->arm64_iMinLine_lg2_szB <= 17); in dis_ARM64_branch_etc()
6714 = 0x8440c000 | ((0xF & (archinfo->arm64_dMinLine_lg2_szB - 2)) << 16) in dis_ARM64_branch_etc()
6715 | ((0xF & (archinfo->arm64_iMinLine_lg2_szB - 2)) << 0); in dis_ARM64_branch_etc()
6748 vassert(archinfo->arm64_iMinLine_lg2_szB >= 2 in dis_ARM64_branch_etc()
6749 && archinfo->arm64_iMinLine_lg2_szB <= 17); in dis_ARM64_branch_etc()
6753 ULong lineszB = 1ULL << archinfo->arm64_iMinLine_lg2_szB; in dis_ARM64_branch_etc()
[all …]
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| D | guest_amd64_toIR.c | 15945 const VexArchInfo* archinfo, in dis_ESC_0F__SSE4() argument
16012 && 0 != (archinfo->hwcaps & VEX_HWCAPS_AMD64_BMI)) { in dis_ESC_0F__SSE4()
16073 && 0 != (archinfo->hwcaps & VEX_HWCAPS_AMD64_LZCNT)) { in dis_ESC_0F__SSE4()
19344 const VexArchInfo* archinfo, in dis_ESC_NONE() argument
20452 && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) { in dis_ESC_NONE()
20472 && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) { in dis_ESC_NONE()
21055 const VexArchInfo* archinfo, in dis_ESC_0F() argument
21108 if (modrm == 0xD0 && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) { in dis_ESC_0F()
21127 if (modrm == 0xD5 && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) { in dis_ESC_0F()
21139 if (modrm == 0xD6 && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) { in dis_ESC_0F()
[all …]
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| D | guest_x86_toIR.c | 8077 const VexArchInfo* archinfo, in disInstr_X86_WRK() argument
8469 if (archinfo->hwcaps == 0/*baseline, no sse at all*/) in disInstr_X86_WRK()
8480 if (archinfo->hwcaps == VEX_HWCAPS_X86_MMXEXT/*integer only sse1 subset*/) in disInstr_X86_WRK()
9094 if (archinfo->hwcaps == VEX_HWCAPS_X86_MMXEXT/*integer only sse1 subset*/) in disInstr_X86_WRK()
9546 if (0 == (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2)) in disInstr_X86_WRK()
11789 if (0 == (archinfo->hwcaps & VEX_HWCAPS_X86_SSE3)) in disInstr_X86_WRK()
12938 && 0 != (archinfo->hwcaps & VEX_HWCAPS_X86_LZCNT)) { in disInstr_X86_WRK()
14845 if (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2) { in disInstr_X86_WRK()
14850 if (archinfo->hwcaps & VEX_HWCAPS_X86_SSE1) { in disInstr_X86_WRK()
14855 if (archinfo->hwcaps & VEX_HWCAPS_X86_MMXEXT) { in disInstr_X86_WRK()
[all …]
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| D | guest_arm_toIR.c | 14438 const VexArchInfo* archinfo, in decode_NV_instruction() argument
14562 if (archinfo->hwcaps & VEX_HWCAPS_ARM_NEON) { in decode_NV_instruction()
14594 const VexArchInfo* archinfo, in disInstr_ARM_WRK() argument
14729 Bool ok = decode_NV_instruction(&dres, archinfo, insn); in disInstr_ARM_WRK()
17424 const VexArchInfo* archinfo, in disInstr_THUMB_WRK() argument
21846 if (archinfo->hwcaps & VEX_HWCAPS_ARM_NEON) { in disInstr_THUMB_WRK()
22023 const VexArchInfo* archinfo, in disInstr_ARM() argument
22048 archinfo, abiinfo, sigill_diag_IN ); in disInstr_ARM()
22053 archinfo, abiinfo, sigill_diag_IN ); in disInstr_ARM()
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| D | guest_ppc_toIR.c | 18864 const VexArchInfo* archinfo, in disInstr_PPC_WRK() argument
18881 UInt hwcaps = archinfo->hwcaps; in disInstr_PPC_WRK()
19833 if (dis_cache_manage( theInstr, &dres, archinfo )) in disInstr_PPC_WRK()
20355 const VexArchInfo* archinfo, in disInstr_PPC() argument
20363 UInt hwcaps_guest = archinfo->hwcaps; in disInstr_PPC()
20403 delta, archinfo, abiinfo, sigill_diag_IN); in disInstr_PPC()
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| D | guest_s390_toIR.c | 16659 const VexArchInfo *archinfo, in disInstr_S390() argument
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