| /external/valgrind/none/tests/mips64/ |
| D | rotate_swap.stdout.exp-mips64r2 | 2 drotr :: in 0x2000ffffffffffff, out 0xffff2000ffffffff, SA 16
3 drotr :: in 0xffff0000ffffffff, out 0xffffffff0000ffff, SA 16
4 drotr :: in 0x2000ffffffffffff, out 0xff2000ffffffffff, SA 8
5 drotr :: in 0x2000ffffffffffff, out 0xf2000fffffffffff, SA 4
6 drotr :: in 0x2000ffffffffffff, out 0xf90007ffffffffff, SA 5
7 drotr :: in 0x31415927ffffffff, out 0xffcc505649ffffff, SA 10
8 drotr :: in 0x2000ffffffffffff, out 0xf2000fffffffffff, SA 4
9 drotr :: in 0x2000ffffffffffff, out 0x2000ffffffffffff, SA 0
10 drotr :: in 0xeeeeffffffffffff, out 0xffffeeeeffffffff, SA 16
11 drotr :: in 0x2000ffffffffbbbb, out 0xffff77764001ffff, SA 31
[all …]
|
| D | shift_instructions.stdout.exp-mips64r2 | 1 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
2 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
3 drotr $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
4 drotr $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
5 drotr $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
6 drotr $t2, $t3, 0x1f :: rt 0x257ad5400000000, rs 0x12bd6aa, imm 0x001f
7 drotr $a0, $a1, 0x0f :: rt 0xad54000000000257, rs 0x12bd6aa, imm 0x000f
8 drotr $s0, $s1, 0x03 :: rt 0x4000000000257ad5, rs 0x12bd6aa, imm 0x0003
9 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
10 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
|
| /external/llvm/test/MC/Mips/ |
| D | mips_directives.s | 74 # CHECK: drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba]
76 drotr $9, $6, 30
|
| D | mips64-alu-instructions.s | 76 # CHECK: drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00]
101 drotr $9, $6, 20
|
| /external/llvm/test/MC/Mips/mips64/ |
| D | invalid-mips64r2.s | 9 …drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm/test/CodeGen/Mips/ |
| D | mips64shift.ll | 88 ; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
97 ; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
|
| /external/llvm/test/MC/Mips/mips5/ |
| D | invalid-mips64r2.s | 14 …drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/v8/test/cctest/ |
| D | test-disasm-mips64.cc | 501 COMPARE(drotr(a0, a1, 0), in TEST()
503 COMPARE(drotr(s0, s1, 8), in TEST()
505 COMPARE(drotr(a6, a7, 24), in TEST()
507 COMPARE(drotr(v0, v1, 31), in TEST()
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 91 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x…
92 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| D | valid.s | 91 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x…
92 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 91 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x…
92 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| D | mips64r2_le.txt | 86 # CHECK: drotr $20, $27, 6
|
| D | mips64r2.txt | 86 # CHECK: drotr $20, $27, 6
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| D | valid-mips64r5-el.txt | 120 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
121 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
|
| D | valid-mips64r5.txt | 120 0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
121 0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-mips64r2-el.txt | 123 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
124 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
|
| D | valid-mips64r2.txt | 123 0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
124 0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| D | valid-mips64r3.txt | 120 0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
121 0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
|
| D | valid-mips64r3-el.txt | 120 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
121 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 165 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
|
| /external/v8/src/mips64/ |
| D | assembler-mips64.h | 807 void drotr(Register rd, Register rt, uint16_t sa);
|
| D | assembler-mips64.cc | 1739 void Assembler::drotr(Register rd, Register rt, uint16_t sa) { in drotr() function in v8::internal::Assembler
|
| D | macro-assembler-mips64.cc | 1035 drotr(rd, rs, rt.imm64_); in Dror()
|