| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | shl.ll | 141 ; GP64: dsllv $2, $4, $1
154 ; M3: dsllv $[[T1:[0-9]+]], $5, $[[T0]]
158 ; M3: dsllv $[[T4:[0-9]+]], $4, $[[T0]]
172 ; GP64-NOT-R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]]
177 ; GP64-NOT-R6: dsllv $3, $5, $[[T0]]
184 ; 64R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]]
192 ; 64R6: dsllv $[[T9:[0-9]+]], $5, $[[T0]]
|
| D | lshr.ll | 149 ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
163 ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
175 ; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
|
| D | ashr.ll | 156 ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
170 ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
191 ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]]
|
| /external/valgrind/none/tests/mips64/ |
| D | shift_instructions.stdout.exp-mips64 | 4097 dsllv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4
4098 dsllv $s0, $s1, $s2 :: rd 0x257ad5400000000, rs 0x12bd6aa, rt 0xa2a6ec661ba84121
4099 dsllv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03
4100 dsllv $s0, $s1, $s2 :: rd 0x9558980000000000, rs 0x7e876382d2ab13, rt 0x614d9b445f12236b
4101 dsllv $t0, $t1, $t2 :: rd 0x2608edb8000000, rs 0x9823b6e, rt 0xffffffffb8757bda
4102 dsllv $s0, $s1, $s2 :: rd 0x1e60000000000000, rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75
4103 dsllv $t0, $t1, $t2 :: rd 0x64db200000000000, rs 0xd4326d9, rt 0xffffffffbcb4666d
4104 dsllv $s0, $s1, $s2 :: rd 0xb5a97ec000000000, rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666
4105 dsllv $t0, $t1, $t2 :: rd 0x476dc0000000000, rs 0x130476dc, rt 0xffffffffa2f33668
4106 dsllv $s0, $s1, $s2 :: rd 0x51433bda81000000, rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17
[all …]
|
| D | shift_instructions.stdout.exp-mips64r2 | 8705 dsllv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4
8706 dsllv $s0, $s1, $s2 :: rd 0x257ad5400000000, rs 0x12bd6aa, rt 0xa2a6ec661ba84121
8707 dsllv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03
8708 dsllv $s0, $s1, $s2 :: rd 0x9558980000000000, rs 0x7e876382d2ab13, rt 0x614d9b445f12236b
8709 dsllv $t0, $t1, $t2 :: rd 0x2608edb8000000, rs 0x9823b6e, rt 0xffffffffb8757bda
8710 dsllv $s0, $s1, $s2 :: rd 0x1e60000000000000, rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75
8711 dsllv $t0, $t1, $t2 :: rd 0x64db200000000000, rs 0xd4326d9, rt 0xffffffffbcb4666d
8712 dsllv $s0, $s1, $s2 :: rd 0xb5a97ec000000000, rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666
8713 dsllv $t0, $t1, $t2 :: rd 0x476dc0000000000, rs 0x130476dc, rt 0xffffffffa2f33668
8714 dsllv $s0, $s1, $s2 :: rd 0x51433bda81000000, rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17
[all …]
|
| /external/v8/test/cctest/ |
| D | test-disasm-mips64.cc | 415 COMPARE(dsllv(a0, a1, a2), in TEST()
417 COMPARE(dsllv(s0, s1, s2), in TEST()
419 COMPARE(dsllv(a6, a7, t0), in TEST()
421 COMPARE(dsllv(v0, v1, fp), in TEST()
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 82 …dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
85 …dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| D | mips64_le.txt | 29 # CHECK: dsllv $gp, $27, $24
|
| D | mips64r2_le.txt | 29 # CHECK: dsllv $gp, $27, $24
|
| D | mips64r2.txt | 29 # CHECK: dsllv $gp, $27, $24
|
| D | mips64.txt | 32 # CHECK: dsllv $gp, $27, $24
|
| /external/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 86 …dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
89 …dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
|
| /external/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 86 …dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
89 …dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
|
| /external/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 91 …dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
94 …dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 100 …dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
103 …dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| D | valid.s | 100 …dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
103 …dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 100 …dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
103 …dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
|
| /external/llvm/test/CodeGen/Mips/ |
| D | mips64shift.ll | 5 ; CHECK: dsllv
|
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| D | valid-mips3.txt | 75 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
78 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
|
| D | valid-mips3-el.txt | 75 0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
78 0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64.txt | 91 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
94 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
|
| D | valid-mips64-el.txt | 91 0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
94 0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| D | valid-mips4-el.txt | 79 0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
82 0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
|
| D | valid-mips4.txt | 79 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
82 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips3.s | 30 …dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
|