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/external/valgrind/none/tests/mips64/
Dshift_instructions.stdout.exp-mips646657 dsra32 $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
6658 dsra32 $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
6659 dsra32 $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
6660 dsra32 $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
6661 dsra32 $t0, $t1, 0x00 :: rt 0x0, rs 0x12bd6aa, imm 0x0000
6662 dsra32 $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
6663 dsra32 $a0, $a1, 0x0f :: rt 0x0, rs 0x12bd6aa, imm 0x000f
6664 dsra32 $s0, $s1, 0x03 :: rt 0x0, rs 0x12bd6aa, imm 0x0003
6665 dsra32 $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
6666 dsra32 $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
Dshift_instructions.stdout.exp-mips64r211265 dsra32 $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
11266 dsra32 $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
11267 dsra32 $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
11268 dsra32 $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
11269 dsra32 $t0, $t1, 0x00 :: rt 0x0, rs 0x12bd6aa, imm 0x0000
11270 dsra32 $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
11271 dsra32 $a0, $a1, 0x0f :: rt 0x0, rs 0x12bd6aa, imm 0x000f
11272 dsra32 $s0, $s1, 0x03 :: rt 0x0, rs 0x12bd6aa, imm 0x0003
11273 dsra32 $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
11274 dsra32 $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
/external/llvm/test/MC/Mips/mips3/
Dvalid.s89 …dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
90 …dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
/external/llvm/test/MC/Mips/mips4/
Dvalid.s93 …dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
94 …dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
/external/llvm/test/MC/Mips/mips5/
Dvalid.s93 …dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
94 …dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
/external/llvm/test/MC/Mips/mips64/
Dvalid.s98 …dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
99 …dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
/external/llvm/test/MC/Mips/
Dmips64shift.ll37 ; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s107 …dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
108 …dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s107 …dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
108 …dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s107 …dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
108 …dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s34 …dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
35 …dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
Dinvalid-mips5.s34 …dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
35 …dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips4.s35 …dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
36 …dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips3.s38 …dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
39 …dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips4.s37 …dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
38 …dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips5.s36 …dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
37 …dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Disassembler/Mips/mips3/
Dvalid-mips3.txt82 0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10
83 0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10
Dvalid-mips3-el.txt82 0xbf 0xe2 0x1c 0x00 # CHECK: dsra32 $gp, $gp, 10
83 0xbf 0xe2 0x12 0x00 # CHECK: dsra32 $gp, $18, 10
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64.txt98 0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10
99 0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10
Dvalid-mips64-el.txt98 0xbf 0xe2 0x1c 0x00 # CHECK: dsra32 $gp, $gp, 10
99 0xbf 0xe2 0x12 0x00 # CHECK: dsra32 $gp, $18, 10
/external/llvm/test/MC/Disassembler/Mips/mips4/
Dvalid-mips4-el.txt86 0xbf 0xe2 0x1c 0x00 # CHECK: dsra32 $gp, $gp, 10
87 0xbf 0xe2 0x12 0x00 # CHECK: dsra32 $gp, $18, 10
Dvalid-mips4.txt86 0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10
87 0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-mips64r5-el.txt101 0xbf 0xe2 0x1c 0x00 # CHECK: dsra32 $gp, $gp, 10
102 0xbf 0xe2 0x12 0x00 # CHECK: dsra32 $gp, $18, 10
Dvalid-mips64r5.txt101 0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10
102 0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-mips64r2-el.txt104 0xbf 0xe2 0x1c 0x00 # CHECK: dsra32 $gp, $gp, 10
105 0xbf 0xe2 0x12 0x00 # CHECK: dsra32 $gp, $18, 10

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