Searched refs:dstReg (Results 1 – 7 of 7) sorted by relevance
/external/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.cpp | 150 unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ? in eliminateFrameIndex() local 157 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset); in eliminateFrameIndex() 160 dstReg).addReg(FrameReg).addReg(dstReg); in eliminateFrameIndex() 164 dstReg).addReg(FrameReg).addImm(Offset); in eliminateFrameIndex() 167 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true); in eliminateFrameIndex() 204 unsigned dstReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local 206 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset); in eliminateFrameIndex() 209 dstReg).addReg(FrameReg).addReg(dstReg); in eliminateFrameIndex() 211 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true); in eliminateFrameIndex()
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/external/mesa3d/src/mesa/program/ |
D | nvfragparse.c | 667 struct prog_dst_register *dstReg) in Parse_CondCodeMask() argument 670 dstReg->CondMask = COND_EQ; in Parse_CondCodeMask() 672 dstReg->CondMask = COND_GE; in Parse_CondCodeMask() 674 dstReg->CondMask = COND_GT; in Parse_CondCodeMask() 676 dstReg->CondMask = COND_LE; in Parse_CondCodeMask() 678 dstReg->CondMask = COND_LT; in Parse_CondCodeMask() 680 dstReg->CondMask = COND_NE; in Parse_CondCodeMask() 682 dstReg->CondMask = COND_TR; in Parse_CondCodeMask() 684 dstReg->CondMask = COND_FL; in Parse_CondCodeMask() 699 dstReg->CondSwizzle = MAKE_SWIZZLE4(swz[0], swz[1], swz[2], swz[3]); in Parse_CondCodeMask() [all …]
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D | prog_execute.c | 481 const struct prog_dst_register *dstReg = &(inst->DstReg); in store_vector4() local 483 GLuint writeMask = dstReg->WriteMask; in store_vector4() 485 GLfloat *dst = get_dst_register_pointer(dstReg, machine); in store_vector4() 503 if (dstReg->CondMask != COND_TR) { in store_vector4() 506 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 0)], in store_vector4() 507 dstReg->CondMask)) in store_vector4() 511 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 1)], in store_vector4() 512 dstReg->CondMask)) in store_vector4() 516 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 2)], in store_vector4() 517 dstReg->CondMask)) in store_vector4() [all …]
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D | prog_print.c | 566 const struct prog_dst_register *dstReg, in fprint_dst_reg() argument 571 reg_string((gl_register_file) dstReg->File, in fprint_dst_reg() 572 dstReg->Index, mode, dstReg->RelAddr, prog, in fprint_dst_reg() 574 _mesa_writemask_string(dstReg->WriteMask)); in fprint_dst_reg() 576 if (dstReg->CondMask != COND_TR) { in fprint_dst_reg() 578 _mesa_condcode_string(dstReg->CondMask), in fprint_dst_reg() 579 _mesa_swizzle_string(dstReg->CondSwizzle, in fprint_dst_reg() 585 _mesa_register_file_name((gl_register_file) dstReg->File), in fprint_dst_reg() 586 dstReg->Index, in fprint_dst_reg() 587 _mesa_writemask_string(dstReg->WriteMask)); in fprint_dst_reg()
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D | nvvertparse.c | 553 Parse_MaskedDstReg(struct parse_state *parseState, struct prog_dst_register *dstReg) in Parse_MaskedDstReg() argument 564 dstReg->File = PROGRAM_TEMPORARY; in Parse_MaskedDstReg() 567 dstReg->Index = idx; in Parse_MaskedDstReg() 571 dstReg->File = PROGRAM_OUTPUT; in Parse_MaskedDstReg() 574 dstReg->Index = idx; in Parse_MaskedDstReg() 580 dstReg->File = PROGRAM_ENV_PARAM; in Parse_MaskedDstReg() 583 dstReg->Index = idx; in Parse_MaskedDstReg() 603 dstReg->WriteMask = 0; in Parse_MaskedDstReg() 606 dstReg->WriteMask |= WRITEMASK_X; in Parse_MaskedDstReg() 610 dstReg->WriteMask |= WRITEMASK_Y; in Parse_MaskedDstReg() [all …]
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D | program_parse.y | 203 %type <dst_reg> dstReg maskedDstReg maskedAddrReg 634 maskedDstReg: dstReg optionalMask optionalCcMask 860 dstReg: resultBinding
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | AMDILCFGStructurizer.cpp | 3150 RegiT dstReg, RegiT src1Reg, in insertCompareInstrBefore() 3157 MachineInstrBuilder(newInstr).addReg(dstReg, RegState::Define); //set target in insertCompareInstrBefore()
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