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Searched refs:emitIntExt (Results 1 – 2 of 2) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp120 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
121 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
1010 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
1018 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
1246 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1309 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) in selectIntExt()
1375 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() function in MipsFastISel
1382 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() function in MipsFastISel
1385 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); in emitIntExt()
1435 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned)) in getRegEnsuringSimpleIntegerWidening()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1134 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1225 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2216 SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*IsZExt=*/true); in emitCompareAndBranch()
2792 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP()
2959 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
2969 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
3730 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
3942 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
4049 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
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