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/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-xfail-mips64r2.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
38 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
40 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
43 0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
49 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
55 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-xfail-mips64r5.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
38 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
40 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
43 0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
49 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
55 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-xfail-mips64r3.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
38 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
40 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
43 0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
49 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
55 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips32r5/
Dvalid-xfail-mips32r5.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
38 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
40 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
43 0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
53 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
54 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
61 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips32r3/
Dvalid-xfail-mips32r3.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
38 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
40 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
43 0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
53 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
54 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
61 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips32r2/
Dvalid-xfail-mips32r2.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
38 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
40 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
43 0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
53 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
54 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
61 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-xfail.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
33 0x4d 0x9e 0x93 0x1e # CHECK: alnv.ps $f12, $f18, $f30, $8
39 0x46 0xde 0xa8 0x3b # CHECK: c.ngl.ps $f21, $f30
41 0x46 0xc6 0xf5 0x3f # CHECK: c.ngt.ps $fcc5, $f30, $f6
51 0x46 0xc0 0x0f 0xa8 # CHECK: cvt.s.pl $f30, $f1
69 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
72 0x46 0xde 0x4e 0x6c # CHECK: pll.ps $f25, $f9, $f30
[all …]
/external/llvm/test/MC/Mips/
Dmips-reginfo-fp32.s33 # abs.d - Reads from $f30 and $f31 and writes to $f30 and $f31.
34 abs.d $f30,$f30
Dmips-reginfo-fp64.s55 # abs.d - Reads from $f30 and writes to $f30.
56 abs.d $f30,$f30
/external/llvm/test/MC/Disassembler/Mips/mips4/
Dvalid-xfail-mips4.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
37 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
40 0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
/external/llvm/test/MC/Mips/mips4/
Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
29 cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Dvalid.s46 c.sf.d $f30,$f0
60 cvt.s.l $f15,$f30
143 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
162 movt.s $f30,$f2,$fcc1
166 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
173 mul.s $f30,$f10,$f2
184 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
263 trunc.w.s $f28,$f30
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
29 cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
29 cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
29 cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips5-wrong-error.s10 … alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
20 … c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
22 … c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 … pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
46 … pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Disassembler/Mips/mips32/
Dvalid-xfail-mips32.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
/external/llvm/test/MC/Mips/mips5/
Dvalid.s46 c.sf.d $f30,$f0
60 cvt.s.l $f15,$f30
144 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
163 movt.s $f30,$f2,$fcc1
167 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
174 mul.s $f30,$f10,$f2
185 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
265 trunc.w.s $f28,$f30
/external/llvm/test/MC/Mips/mips64/
Dvalid.s46 c.sf.d $f30,$f0
62 cvt.s.l $f15,$f30
153 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
173 movt.s $f30,$f2,$fcc1
179 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
188 mul.s $f30,$f10,$f2
199 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
282 trunc.w.s $f28,$f30
/external/llvm/test/CodeGen/PowerPC/
Dvsx-spill.ll10 …19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
31 …19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
51 …9},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1}…
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips32r2.s14 …nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s46 c.sf.d $f30,$f0
124 movt.s $f30,$f2,$fcc1
140 mul.s $f30,$f10,$f2
151 nmsub.d $f30,$f8,$f16,$f30
238 trunc.w.s $f28,$f30
/external/llvm/test/MC/Mips/mips32r5/
Dvalid.s46 c.sf.d $f30,$f0
124 movt.s $f30,$f2,$fcc1
140 mul.s $f30,$f10,$f2
151 nmsub.d $f30,$f8,$f16,$f30
238 trunc.w.s $f28,$f30
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s46 c.sf.d $f30,$f0
124 movt.s $f30,$f2,$fcc1
140 mul.s $f30,$f10,$f2
151 nmsub.d $f30,$f8,$f16,$f30
238 trunc.w.s $f28,$f30
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll22 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
56 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
86 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
114 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()

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