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Searched refs:fabd (Results 1 – 20 of 20) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-scalar-abs.s17 fabd s29, s24, s20
18 fabd d29, d24, d20
Dneon-aba-abd.s71 fabd v0.2s, v1.2s, v2.2s
72 fabd v31.4s, v15.4s, v16.4s
73 fabd v7.2d, v8.2d, v25.2d
Dneon-diagnostics.s338 fabd v0.2s, v1.4s, v2.2d
339 fabd v0.4h, v1.4h, v2.4h
7326 fabd s29, d24, s20
7327 fabd d29, s24, d20
Darm64-advsimd.s308 fabd.2s v0, v0, v0
378 ; CHECK: fabd.2s v0, v0, v0 ; encoding: [0x00,0xd4,0xa0,0x2e]
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-aba-abd.ll211 declare <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float>, <2 x float>)
215 %abd = call <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float> %lhs, <2 x float> %rhs)
216 ; CHECK: fabd v0.2s, v0.2s, v1.2s
220 declare <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float>, <4 x float>)
224 %abd = call <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float> %lhs, <4 x float> %rhs)
225 ; CHECK: fabd v0.4s, v0.4s, v1.4s
229 declare <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double>, <2 x double>)
233 %abd = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %lhs, <2 x double> %rhs)
234 ; CHECK: fabd v0.2d, v0.2d, v1.2d
Darm64-vabs.ll139 ;CHECK: fabd.2s
142 %tmp3 = call <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
148 ;CHECK: fabd.4s
151 %tmp3 = call <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
157 ;CHECK: fabd.2d
160 … %tmp3 = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
164 declare <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float>, <2 x float>) nounwind readnone
165 declare <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float>, <4 x float>) nounwind readnone
166 declare <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double>, <2 x double>) nounwind readnone
763 ; CHECK: fabd s0, s0, s1
[all …]
Darm64-neon-add-sub.ll184 ; CHECK: fabd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
185 %1 = tail call <1 x double> @llvm.aarch64.neon.fabd.v1f64(<1 x double> %a, <1 x double> %b)
236 declare <1 x double> @llvm.aarch64.neon.fabd.v1f64(<1 x double>, <1 x double>)
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt151 # CHECK: fabd v1.4s, v31.4s, v16.4s
2634 # CHECK: fabd s29, s24, s20
2635 # CHECK: fabd d29, d24, d20
Darm64-advsimd.txt293 # CHECK: fabd.2s v0, v0, v0
/external/valgrind/none/tests/arm64/
Dfp_and_simd.c2116 GEN_BINARY_TEST(fabd, 2d, 2d, 2d)
2117 GEN_BINARY_TEST(fabd, 4s, 4s, 4s)
2118 GEN_BINARY_TEST(fabd, 2s, 2s, 2s)
Dfp_and_simd.stdout.exp26 fabd d2, d11, d29 570037914d04ab3d05d75ec6f616ee9a 17a0dc273ba9f8030a52741849e54740 f6f2b14fbb3…
27 fabd s2, s11, s29 e8c72e865de41295f2db8f44cbbf37e2 fcd015ff8f2e73a3a0fae06860b606c7 f34428d9c88…
28 fabd v9.2d, v7.2d, v8.2d f9da7f07e00794eb00b0940ba5e08516 be625608d5abd787f5c90ee73af5d7c0 79da7…
29 fabd v9.4s, v7.4s, v8.4s ddb5cd8016d27d057796e0861576e44f 4e94ec120b386f523bfcd80321664d3e 5db5c…
30 fabd v9.2s, v7.2s, v8.2s 3d3cc0784c2f856363d9810079bbabd9 125934a781e479d33d431279cce48fce 00000…
/external/vixl/test/
Dtest-simulator-a64.cc3773 DEFINE_TEST_NEON_3SAME_FP(fabd, Basic)
3810 DEFINE_TEST_NEON_3SAME_FP_SCALAR(fabd, Basic)
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc2665 case NEON_FABD: fabd(vf, rd, rn, rm); break; in VisitNEON3Same()
3561 case NEON_FABD_scalar: fabd(vf, rd, rn, rm); break; in VisitNEONScalar3Same()
Dsimulator-a64.h2433 LogicVRegister fabd(VectorFormat vform,
Dmacro-assembler-a64.h2098 V(fabd, Fabd) \
Dassembler-a64.h3605 void fabd(const VRegister& vd,
Dlogic-a64.cc4168 LogicVRegister Simulator::fabd(VectorFormat vform, in fabd() function in vixl::Simulator
Dassembler-a64.cc3247 V(fabd, NEON_FABD, NEON_FABD_scalar) \
/external/vixl/doc/
Dsupported-instructions.md1679 void fabd(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2713 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2987 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;