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Searched refs:fminv (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Darm64-fminv.ll6 %min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in)
12 ; CHECK: fminv s0, v0.4s
13 %min = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %in)
20 %min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in)
24 declare float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float>)
25 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
26 declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>)
Darm64-neon-across.ll7 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
439 ; CHECK: fminv s{{[0-9]+}}, {{v[0-9]+}}.4s
441 %0 = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %a)
/external/llvm/test/MC/AArch64/
Dneon-across.s96 fminv s0, v1.4s
Dneon-diagnostics.s3820 fminv b0, v1.16b
3838 fminv h0, v1.8h
3856 fminv d0, v1.2d define
/external/vixl/src/vixl/a64/
Dsimulator-a64.h2494 LogicVRegister fminv(VectorFormat vform,
Dmacro-assembler-a64.h2246 V(fminv, Fminv) \
Dassembler-a64.h2950 void fminv(const VRegister& vd,
Dsimulator-a64.cc2825 case NEON_FMINV: fminv(vf, rd, rn); break; in VisitNEONAcrossLanes()
Dlogic-a64.cc4251 LogicVRegister Simulator::fminv(VectorFormat vform, in fminv() function in vixl::Simulator
Dassembler-a64.cc4029 V(fminv, NEON_FMINV, vd.Is1S()) \
/external/vixl/test/
Dtest-simulator-a64.cc4039 DEFINE_TEST_NEON_ACROSS_FP(fminv, Basic)
/external/vixl/doc/
Dsupported-instructions.md2169 void fminv(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3836 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26538 fminv s2, v23.4s 3ddddea900fd57f6343bd5c5f30359a4 4c029eff6baf4b8b1df6db1b0bfc9b1e 000000000000…