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Searched refs:fmls (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-scalar-by-elem-mla.s24 fmls s2, s3, v4.s[0]
25 fmls s29, s10, v28.s[1]
26 fmls s5, s12, v23.s[2]
27 fmls s7, s17, v26.s[3]
28 fmls d0, d1, v1.d[0] define
29 fmls d30, d11, v1.d[1]
Dnoneon-diagnostics.s17 fmls v3.4s, v12.4s, v17.4s
18 fmls v1.2d, v30.2d, v20.2d
19 fmls v9.2s, v9.2s, v0.2s
Dneon-mla-mls-instructions.s54 fmls v0.2s, v1.2s, v2.2s
55 fmls v0.4s, v1.4s, v2.4s
56 fmls v0.2d, v1.2d, v2.2d
Dneon-2velem.s63 fmls v0.2s, v1.2s, v2.s[2]
64 fmls v0.2s, v1.2s, v22.s[2]
65 fmls v3.4s, v8.4s, v2.s[1]
66 fmls v3.4s, v8.4s, v22.s[3]
67 fmls v0.2d, v1.2d, v2.d[1]
68 fmls v0.2d, v1.2d, v22.d[1]
Dneon-diagnostics.s129 fmls v0.16b, v1.8b, v2.8b
3051 fmls v0.4h, v1.4h, v2.h[2]
3052 fmls v0.8h, v1.8h, v2.h[2]
3053 fmls v0.2s, v1.2s, v2.s[4]
3054 fmls v0.2s, v1.2s, v22.s[4]
3055 fmls v3.4s, v8.4s, v2.s[4]
3056 fmls v3.4s, v8.4s, v22.s[4]
3057 fmls v0.2d, v1.2d, v2.d[2]
3058 fmls v0.2d, v1.2d, v22.d[2]
6933 fmls s29, h10, v28.s[1]
[all …]
Darm64-advsimd.s326 fmls.2s v0, v0, v0
396 ; CHECK: fmls.2s v0, v0, v0 ; encoding: [0x00,0xcc,0xa0,0x0e]
985 fmls.s s0, s0, v0[3]
986 fmls.d d0, d0, v0[1]
1003 ; CHECK: fmls.s s0, s0, v0[3] ; encoding: [0x00,0x58,0xa0,0x5f]
1004 ; CHECK: fmls.d d0, d0, v0[1] ; encoding: [0x00,0x58,0xc0,0x5f]
1057 fmls.2s v0, v0, v0[0]
1058 fmls.4s v0, v0, v0[1]
1059 fmls.2d v0, v0, v0[1]
1126 ; CHECK: fmls.2s v0, v0, v0[0] ; encoding: [0x00,0x50,0x80,0x0f]
[all …]
/external/llvm/test/CodeGen/AArch64/
Dneon-scalar-by-elem-fma.ll56 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
65 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
75 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
84 ; CHECK: {{fmls d[0-9]+, d[0-9]+, v[0-9]+.d\[0]|fmsub d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+}}
93 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
102 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
Dneon-fma.ll26 ;CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
33 ;CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
40 ;CHECK: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
72 ;CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
79 ;CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
86 ;CHECK: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
126 ;CHECK-NOT: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
Darm64-vmul.ll479 ;CHECK: fmls.2s
490 ;CHECK: fmls.4s
501 ;CHECK: fmls.2d
512 ;CHECK: fmls.2s
523 ;CHECK: fmls.4s
534 ;CHECK: fmls.2d
545 ;CHECK: fmls.2s
555 ;CHECK: fmls.4s
565 ;CHECK: fmls.2d
1901 ; CHECK: fmls.s s0, s1, v2[3]
[all …]
Darm64-neon-2velem.ll427 ; CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
438 ; CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
449 ; CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
460 ; CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
493 ; CHECK: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
504 ; CHECK: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
540 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
551 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
1876 ; CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
1887 ; CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
[all …]
Darm64-neon-2velem-high.ll321 ; CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[{{[0-9]+}}]
332 ; CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
/external/vixl/src/vixl/a64/
Dlogic-a64.cc4082 LogicVRegister Simulator::fmls(VectorFormat vform, in fmls() function in vixl::Simulator
4098 LogicVRegister Simulator::fmls(VectorFormat vform, in fmls() function in vixl::Simulator
4103 fmls<float>(vform, dst, src1, src2); in fmls()
4106 fmls<double>(vform, dst, src1, src2); in fmls()
4312 LogicVRegister Simulator::fmls(VectorFormat vform, in fmls() function in vixl::Simulator
4321 fmls<float>(vform, dst, src1, index_reg); in fmls()
4326 fmls<double>(vform, dst, src1, index_reg); in fmls()
Dsimulator-a64.h1605 LogicVRegister fmls(VectorFormat vform,
2378 LogicVRegister fmls(VectorFormat vform,
2382 LogicVRegister fmls(VectorFormat vform,
Dsimulator-a64.cc2656 case NEON_FMLS: fmls(vf, rd, rn, rm); break; in VisitNEON3Same()
2946 case NEON_FMLS_byelement: Op = &Simulator::fmls; break; in VisitNEONByIndexedElement()
3653 case NEON_FMLS_byelement_scalar: Op = &Simulator::fmls; break; in VisitNEONScalarByIndexedElement()
Dmacro-assembler-a64.h2110 V(fmls, Fmls) \
2329 V(fmls, Fmls) \
Dassembler-a64.h3521 void fmls(const VRegister& vd,
3553 void fmls(const VRegister& vd,
Dassembler-a64.cc3249 V(fmls, NEON_FMLS, 0) \
3514 V(fmls, NEON_FMLS_byelement) \
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt311 # CHECK: fmls.2s v0, v0, v0
1601 # CHECK: fmls.s s0, s0, v0[3]
1602 # CHECK: fmls.d d0, d0, v0[1]
1693 # CHECK: fmls.2s v0, v0, v0[0]
1694 # CHECK: fmls.4s v0, v0, v0[1]
1695 # CHECK: fmls.2d v0, v0, v0[1]
Dneon-instructions.txt80 # CHECK: fmls v31.2s, v31.2s, v31.2s
2325 # CHECK: fmls s3, s5, v7.s[0]
2326 # CHECK: fmls s3, s5, v7.s[3]
2327 # CHECK: fmls s3, s5, v15.s[3]
2328 # CHECK: fmls d0, d4, v8.d[0]
2329 # CHECK: fmls d0, d4, v8.d[1]
/external/vixl/test/
Dtest-simulator-a64.cc3735 DEFINE_TEST_NEON_3SAME_FP(fmls, Basic)
4062 DEFINE_TEST_NEON_FP_BYELEMENT(fmls, Basic, Basic, Basic)
4079 DEFINE_TEST_NEON_FP_BYELEMENT_SCALAR(fmls, Basic, Basic, Basic)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26542 fmls v2.2d, v23.2d, v11.2d beb71a303535c22a4550b549a82fbc9b 4fa5f75779c544e781323d30718bb6e6 fc…
26543 fmls v2.4s, v23.4s, v11.4s dfb7261f93ff40a32f130b0ba3cdf11f f2c317e004b12a0f086e75eafd0c2b9e 1a…
26544 fmls v2.2s, v23.2s, v11.2s cd58cf98fe135a53cc1982e4ac6e5874 86f919a1d9f4f3d54c5e5a7ac5558bfd 85…
26549 fmls d2, d11, v29.d[0] b777ef4a223cb6acbf025b9e05e6b4b6 f1e2596e9ad2847302dcf6c57014111e e88495…
26550 fmls d2, d11, v29.d[1] 48171868557fec4593883662ae006c0c 509c01c18773cf963f55a09bb6cc3604 0e96cd…
26551 fmls s2, s11, v29.s[0] 43e93a600955af0695f709d04dd5de4b 49b5cb83d29bddfc02057e817f08fa07 4d167d…
26552 fmls s2, s11, v29.s[3] 9e75f3e17db59208bbb052c2b1ad9b3d cd06d22086b1fd6564462b510f85cfb8 78c690…
26559 fmls v2.2d, v11.2d, v29.d[0] c19db680d9779f9af70926f001874c5a 3643d33b2c89671becebc911cab8253a …
26561 fmls v2.2d, v11.2d, v29.d[1] b18c47c047fd44dba5189913a885aabd 2cca34a6fc18618b1cca3c9c98611031 …
26562 fmls v2.4s, v11.4s, v29.s[0] 205b7859ebe2bae0d7feea9f3b4b47e6 b8dddbe7b8d6745d2770724e47e1c0cd …
[all …]
/external/vixl/doc/
Dsupported-instructions.md2196 void fmls(const VRegister& vd,
2206 void fmls(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2735 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
4225 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;