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Searched refs:frsqrts (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-frsqrt-frecp.s8 frsqrts v0.2s, v31.2s, v16.2s
9 frsqrts v4.4s, v7.4s, v15.4s
10 frsqrts v29.2d, v2.2d, v5.2d
Dneon-scalar-recip.s19 frsqrts s21, s5, s12
20 frsqrts d8, d22, d18 define
Dneon-diagnostics.s397 frsqrts v0.2d, v1.2d, v2.2s
398 frsqrts v0.4h, v1.4h, v2.4h
3903 frsqrts s21, h5, s12
3904 frsqrts d8, s22, d18 define
Darm64-advsimd.s332 frsqrts.2s v0, v0, v0
403 ; CHECK: frsqrts.2s v0, v0, v0 ; encoding: [0x00,0xfc,0xa0,0x0e]
/external/llvm/test/CodeGen/AArch64/
Darm64-vsqrt.ll37 ;CHECK: frsqrts.2s
40 %tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
46 ;CHECK: frsqrts.4s
49 %tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
55 ;CHECK: frsqrts.2d
58 %tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
62 declare <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
63 declare <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
64 declare <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double>, <2 x double>) nounwind readnone
217 ; CHECK: frsqrts s0, s0, s1
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/external/vixl/src/vixl/a64/
Dsimulator-a64.h2360 LogicVRegister frsqrts(VectorFormat vform,
2364 LogicVRegister frsqrts(VectorFormat vform,
Dlogic-a64.cc3940 LogicVRegister Simulator::frsqrts(VectorFormat vform, in frsqrts() function in vixl::Simulator
3955 LogicVRegister Simulator::frsqrts(VectorFormat vform, in frsqrts() function in vixl::Simulator
3960 frsqrts<float>(vform, dst, src1, src2); in frsqrts()
3963 frsqrts<double>(vform, dst, src1, src2); in frsqrts()
Dsimulator-a64.cc2664 case NEON_FRSQRTS: frsqrts(vf, rd, rn, rm); break; in VisitNEON3Same()
3560 case NEON_FRSQRTS_scalar: frsqrts(vf, rd, rn, rm); break; in VisitNEONScalar3Same()
Dmacro-assembler-a64.h2113 V(frsqrts, Frsqrts) \
Dassembler-a64.h3309 void frsqrts(const VRegister& vd,
Dassembler-a64.cc3246 V(frsqrts, NEON_FRSQRTS, NEON_FRSQRTS_scalar) \
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt171 # CHECK: frsqrts v31.2d, v15.2d, v8.2d
1507 # CHECK: frsqrts s21, s5, s12
1508 # CHECK: frsqrts d8, d22, d18
Darm64-advsimd.txt315 # CHECK: frsqrts.2s v0, v0, v0
/external/vixl/test/
Dtest-simulator-a64.cc3738 DEFINE_TEST_NEON_3SAME_FP(frsqrts, Basic)
3796 DEFINE_TEST_NEON_3SAME_FP_SCALAR(frsqrts, Basic)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26673 frsqrts d2, d11, d29 3a6981d76589b8d982bd58214b7c40f0 99ec360eed34356ccb9b81f11b6ee3df eba76f51…
26674 frsqrts s2, s11, s29 582361c1915ca8e177744c423ad40a20 2ba325970917d9b9f0c9f32ffeb8d9f9 ab593df0…
26675 frsqrts v2.2d, v11.2d, v29.2d 09a1d547c7321eb28466909168184899 67cc4d3be6cc496d83209b5a16fcc83a …
26676 frsqrts v2.4s, v11.4s, v29.4s 527541dccb603f802ea90a00191d9d10 51fa136d46a6a9bc09b65e63a70e5558 …
26677 frsqrts v2.2s, v11.2s, v29.2s 363409f6613a2e7ef94f9c8592b6ad39 ecc0dba2effa1ed9069d1f3ff5c32305 …
/external/vixl/doc/
Dsupported-instructions.md2428 void frsqrts(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2752 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2999 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;