Searched refs:getInstrPredicate (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
461 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { in rewriteT2FrameIndex()
634 return getInstrPredicate(MI, PredReg); in getITInstrPredicate()
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| D | ARMLoadStoreOptimizer.cpp | 936 getInstrPredicate(MI, MyPredReg) == Pred && in isMatchingDecrement()
971 getInstrPredicate(MI, MyPredReg) == Pred && in isMatchingIncrement()
1112 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in MergeBaseUpdateLSMultiple()
1269 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in MergeBaseUpdateLoadStore()
1507 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in FixInvalidRegPairOp()
1626 ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg); in LoadStoreMultipleOpti()
2027 Pred = getInstrPredicate(Op0, PredReg); in CanFormLdStDWord()
2219 if (getInstrPredicate(MI, PredReg) != ARMCC::AL) in RescheduleLoadStoreInstrs()
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| D | Thumb2SizeReduction.cpp | 582 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
686 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
783 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
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| D | ARMBaseInstrInfo.h | 440 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| D | ARMConstantIslandPass.cpp | 1810 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); in optimizeThumb2Branches()
1828 Pred = getInstrPredicate(CmpMI, PredReg); in optimizeThumb2Branches()
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| D | ARMExpandPseudoInsts.cpp | 657 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); in ExpandMOV32BitImm()
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| D | ARMBaseInstrInfo.cpp | 1733 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate() function in llvm
1764 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstruction()
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