Searched refs:halfword (Results 1 – 25 of 50) sorted by relevance
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| /external/libvpx/libvpx/vp8/encoder/arm/armv6/ |
| D | vp8_short_fdct4x4_armv6.asm | 147 lsl r8, r2, #16 ; prepare bottom halfword for scaling
148 asr r2, r2, #4 ; scale top halfword
149 lsl r9, r3, #16 ; prepare bottom halfword for scaling
150 asr r3, r3, #4 ; scale top halfword
151 pkhtb r4, r2, r8, asr #20 ; pack and scale bottom halfword
152 pkhtb r5, r3, r9, asr #20 ; pack and scale bottom halfword
201 lsl r8, r2, #16 ; prepare bottom halfword for scaling
202 asr r2, r2, #4 ; scale top halfword
203 lsl r9, r3, #16 ; prepare bottom halfword for scaling
204 asr r3, r3, #4 ; scale top halfword
[all …]
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| /external/valgrind/docs/internals/ |
| D | s390-opcodes.csv | 6 ah,"add halfword",implemented,
37 ch,"compare halfword",implemented,
98 lh,"load halfword",implemented,
121 mh,"multiply halfword",implemented,
173 sh,"subtract halfword",implemented,
213 sth,"store halfword",implemented,
245 ahi,"add halfword immediate",implemented,
252 chi,"compare halfword immediate",implemented,
254 lhi,"load halfword immediate",implemented,
256 mhi,"multiply halfword immediate",implemented,
[all …]
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | combine_ir.ll | 15 ; CHECK: halfword
18 define void @halfword(i16* nocapture %a) nounwind {
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| /external/libavc/common/arm/ |
| D | ih264_iquant_itrans_recon_dc_a9.s | 125 ldrsh r8, [r0] @load pi2_src[0], SH for signed halfword load
126 ldrh r6, [r6] @load pu2_weight_mat[0] , H for unsigned halfword load
127 ldrh r5, [r5] @load pu2_iscal_mat[0] , H for unsigned halfword load
140 ldrsheq r10, [r0] @ Loads signed halfword pi2_src[0], if r9==1
244 ldrsh r8, [r0] @load pi2_src[0], SH for signed halfword load
245 ldrh r6, [r6] @load pu2_weight_mat[0] , H for unsigned halfword load
246 ldrh r5, [r5] @load pu2_iscal_mat[0] , H for unsigned halfword load
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| D | ih264_ihadamard_scaling_a9.s | 105 ldrh r6, [r3] @ load pu2_weight_mat[0] , H for unsigned halfword load
106 ldrh r7, [r2] @ load pu2_iscal_mat[0] , H for unsigned halfword load
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| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | memory-layout.ll | 23 @halfword = global i16 258, align 1
36 ; ALL-LABEL: halfword:
38 ; ALL: .size halfword, 2
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | int-move-05.ll | 44 ; Check the next halfword up, which should use STHY instead of STH.
64 ; Check the next halfword up, which needs separate address logic.
96 ; Check the next halfword down, which needs separate address logic.
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| D | int-add-01.ll | 29 ; Check the next halfword up, which should use AHY instead of AH.
53 ; Check the next halfword up, which needs separate address logic.
91 ; Check the next halfword down, which needs separate address logic.
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| D | int-mul-01.ll | 29 ; Check the next halfword up, which should use MHY instead of MH.
53 ; Check the next halfword up, which needs separate address logic.
91 ; Check the next halfword down, which needs separate address logic.
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| D | int-sub-07.ll | 29 ; Check the next halfword up, which should use SHY instead of SH.
53 ; Check the next halfword up, which needs separate address logic.
91 ; Check the next halfword down, which needs separate address logic.
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| D | int-conv-05.ll | 1 ; Test sign extensions from a halfword to an i32.
46 ; Check the next halfword up, which needs LHY rather than LH.
68 ; Check the next halfword up, which needs separate address logic.
103 ; Check the next halfword down, which needs separate address logic.
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| D | int-cmp-01.ll | 33 ; Check the next halfword up, which should use CHY instead of CH.
61 ; Check the next halfword up, which needs separate address logic.
105 ; Check the next halfword down, which needs separate address logic.
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| D | int-conv-06.ll | 1 ; Test zero extensions from a halfword to an i32. The tests here
56 ; Check the next halfword up, which needs separate address logic.
91 ; Check the next halfword down, which needs separate address logic.
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| D | int-conv-08.ll | 1 ; Test zero extensions from a halfword to an i64.
55 ; Check the next halfword up, which needs separate address logic.
90 ; Check the next halfword down, which needs separate address logic.
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| D | int-conv-07.ll | 1 ; Test sign extensions from a halfword to an i64.
46 ; Check the next halfword up, which needs separate address logic.
81 ; Check the next halfword down, which needs separate address logic.
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| D | int-cmp-04.ll | 33 ; Check the next halfword up, which needs separate address logic.
77 ; Check the next halfword down, which needs separate address logic.
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| D | int-const-04.ll | 78 ; Check the next halfword up, which is out of range. We prefer STHY
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| D | int-cmp-23.ll | 45 ; Check the next halfword up, which needs separate address logic,
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| D | cond-store-02.ll | 205 ; Check the next halfword up, which should use STHY instead of STH.
239 ; Check the next halfword up, which needs separate address logic.
275 ; Check the next halfword down, which needs separate address logic.
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| D | int-cmp-22.ll | 84 ; Check the next halfword up, which needs separate address logic,
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| /external/llvm/test/MC/Disassembler/Hexagon/ |
| D | memop.txt | 22 # Operation on memory halfword
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| D | ld.txt | 102 # Load halfword
120 # Load halfword conditionally
192 # Load unsigned halfword
210 # Load unsigned halfword conditionally
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| D | nv_st.txt | 71 # Store new-value halfword
94 # Store new-value halfword conditionally
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| D | st.txt | 116 # Store halfword
152 # Store halfword conditionally
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | vec_extload.ll | 56 ; Same as v16si8_sext_in_reg, expands to load halfword (lha) and
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