Searched refs:hasV6Ops (Results 1 – 10 of 10) sorted by relevance
290 bool hasV6Ops() const { return HasV6Ops; } in hasV6Ops() function328 return HasDataBarrier || (hasV6Ops() && !isThumb()); in hasAnyDataBarrier()
51 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) in copyPhysReg()
246 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD())); in initSubtargetFeatures()
2636 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? in Select()2652 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? in Select()2668 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? in Select()2684 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? in Select()
2674 bool hasV6Ops = Subtarget->hasV6Ops(); in ARMEmitIntExt() local2678 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt]; in ARMEmitIntExt()
581 !STI->hasV6Ops()) { in MergeOps()1998 unsigned ReqAlign = STI->hasV6Ops() in CanFormLdStDWord()
672 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() in ARMTargetLowering()704 if (!Subtarget->hasV6Ops()) in ARMTargetLowering()817 if (!Subtarget->hasV6Ops()) { in ARMTargetLowering()930 if (Subtarget->hasV6Ops()) in ARMTargetLowering()1171 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4); in shouldAlignPointerArgs()2730 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && in LowerATOMIC_FENCE()9563 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) { in PerformShiftCombine()10441 if (!Subtarget->hasV6Ops()) in ExpandInlineAsm()11009 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) { in makeDMB()
547 else if (Subtarget->hasV6Ops()) in getArchForCPU()
193 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,195 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
258 bool hasV6Ops() const { in hasV6Ops() function in __anonef5d38c20111::ARMAsmParser8563 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && in checkTargetMatchPredicate()