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Searched refs:i7 (Results 1 – 25 of 86) sorted by relevance

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/external/llvm/test/Transforms/InstCombine/
Dapint-and1.ll37 define i7 @test5(i7 %A, i7* %P) {
38 %B = or i7 %A, 3
39 %C = xor i7 %B, 12
40 store i7 %C, i7* %P
41 %r = and i7 %C, 3
42 ret i7 %r
45 define i7 @test6(i7 %A, i7 %B) {
47 %t0 = xor i7 %A, -1
48 %t1 = and i7 %t0, %B
49 %r = xor i7 %t1, -1
[all …]
Dapint-call-cast-target.ll8 ; CHECK: %[[call:.*]] = call i7* @ctime(i999* null)
9 ; CHECK: %[[cast:.*]] = ptrtoint i7* %[[call]] to i32
12 %tmp = call i32 bitcast (i7* (i999*)* @ctime to i32 (i99*)*)( i99* null )
16 define i7* @ctime(i999*) {
17 ; CHECK-LABEL: define i7* @ctime(
19 ; CHECK: %[[cast:.*]] = inttoptr i32 %[[call]] to i7*
21 %tmp = call i7* bitcast (i32 ()* @main to i7* ()*)( )
22 ret i7* %tmp
Dapint-xor1.ll32 define i7 @test5(i7 %A) {
34 %t1 = or i7 %A, 23
35 %r = xor i7 %t1, 23
36 ret i7 %r
39 define i7 @test6(i7 %A) {
40 %t1 = xor i7 %A, 23
41 %r = xor i7 %t1, 23
42 ret i7 %r
Dapint-and-or-and.ll45 define i7 @or_test2(i7 %X, i7 %Y) {
46 %A = shl i7 %X, 6
47 %B = or i7 %A, 64 ;; This cannot include any bits from X!
48 ret i7 %B
Dapint-or1.ll8 define i7 @test0(i7 %X) {
9 %Y = or i7 %X, 0
10 ret i7 %Y
Dapint-shift.ll14 define i41 @test2(i7 %X) {
15 %A = zext i7 %X to i41 ; <i41> [#uses=1]
29 define i39 @test4(i7 %X) {
30 %A = zext i7 %X to i39 ; <i39> [#uses=1]
75 define i7 @test8(i7 %A) {
76 %B = shl i7 %A, 4 ; <i7> [#uses=1]
77 %C = shl i7 %B, 3 ; <i7> [#uses=1]
78 ret i7 %C
/external/v8/test/mjsunit/compiler/
Dregress-177883.js68 …var i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i12 = 0, i13 = 0, i1…
76 i7 = i4 + 8 | 0;
77 HEAPF32[i7 >> 2] = 0.0;
95 HEAPF32[i7 >> 2] = d18;
100 HEAPF32[i7 >> 2] = +HEAPF32[i14 >> 2];
107 HEAPF32[i7 >> 2] = d17;
114 HEAPF32[i7 >> 2] = d18;
121 HEAPF32[i7 >> 2] = d17;
126 HEAPF32[i7 >> 2] = +HEAPF32[i11 >> 2];
133 HEAPF32[i7 >> 2] = d18;
[all …]
/external/clang/test/CodeGen/
Darm64-arguments.c297 int f38_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f38_stack() argument
308 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f38_stack()
350 int f39_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f39_stack() argument
361 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f39_stack()
405 int f40_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f40_stack() argument
416 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f40_stack()
460 int f41_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f41_stack() argument
471 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f41_stack()
517 int f42_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f42_stack() argument
524 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f42_stack()
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dmulwide.ll72 define i64 @mulwideu7(i7 %a, i7 %b) {
75 %val0 = zext i7 %a to i64
76 %val1 = zext i7 %b to i64
83 define i64 @mulwides7(i7 %a, i7 %b) {
86 %val0 = sext i7 %a to i64
87 %val1 = sext i7 %b to i64
/external/llvm/test/CodeGen/SPARC/
D64spill.ll13 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
24 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
35 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
47 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
58 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
69 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
80 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
91 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
102 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
113 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
/external/llvm/test/CodeGen/X86/
D2008-09-09-LinearScanBug.ll10 br label %forcond1.preheader.i.i7
12 forcond1.preheader.i.i7: ; preds = %forinc6.i.i25, %entry
17 forinc.i.i11: ; preds = %forcond1.backedge.i.i20, %forcond1.preheader.i.i7
18 …%p_87.addr.02.i.i8 = phi i32 [ %p_87.addr.15.i.i5, %forcond1.preheader.i.i7 ], [ %p_87.addr.0.be.i…
35 forinc6.i.i25: ; preds = %forcond1.backedge.i.i20, %forcond1.preheader.i.i7
36 …%p_87.addr.0.lcssa.i.i21 = phi i32 [ %p_87.addr.15.i.i5, %forcond1.preheader.i.i7 ], [ %p_87.addr.…
40 br i1 %phitmp.i.i24, label %func_106.exit27, label %forcond1.preheader.i.i7
D2006-08-07-CycleInDAG.ll17 %tmp13.i7 = mul i32 %tmp11.i, %n.i ; <i32> [#uses=1]
18 %tmp.i8 = tail call i8* @calloc( i32 %tmp13.i7, i32 4 ) ; <i8*> [#uses=0]
D2009-09-22-CoalescerBug.ll75 br i1 undef, label %bb1.i7, label %quantum_measure.exit
77 bb1.i7: ; preds = %bb17
80 quantum_measure.exit: ; preds = %bb1.i7, %bb17
D2008-02-27-DeadSlotElimBug.ll48 %tmp20.i7 = getelementptr %struct.CompAtom, %struct.CompAtom* %d, i32 0, i32 2 ; <i32*> [#uses=2]
50 %tmp74.i = load i32, i32* %tmp20.i7, align 1 ; <i32> [#uses=1]
54 %tmp88.i = load i32, i32* %tmp20.i7, align 1 ; <i32> [#uses=1]
Ddagcombine-unsafe-math.ll53 %vecext.i7.i155 = extractelement <4 x float> %mul.i.i151, i32 2
54 %add.i.i156 = fadd float %vecext.i7.i155, %add.i10.i154
/external/llvm/test/Transforms/GVN/
Dcrash.ll104 %tmp18.i = load i7*, i7** undef
105 %tmp1 = bitcast i7* %tmp18.i to i8*
109 %tmp2 = bitcast i7* %tmp18.i to i8*
114 %tmp3 = bitcast i7* %tmp18.i to i8*
126 %tmp58.i = load i7*, i7** undef
128 %tmp5 = bitcast i7* %tmp58.i to i8*
/external/libvpx/libvpx/vp8/encoder/arm/armv6/
Dvp8_short_fdct4x4_armv6.asm49 ldrd r8, r9, [r0] ; [i5 | i4] [i7 | i6]
57 ror r9, r9, #16 ; [i6 | i7]
59 qadd16 r6, r8, r9 ; [i5+i6 | i4+i7] = [b1 | a1] without shift
60 qsub16 r7, r8, r9 ; [i5-i6 | i4-i7] = [c1 | d1] without shift
68 smuad r9, r6, lr ; o4 = (i5+i6)*8 + (i4+i7)*8
69 smusd r8, r6, lr ; o6 = (i5+i6)*8 - (i4+i7)*8
186 ldr r9, [r1, #12] ; [i7 | i6]
192 qadd16 r5, r9, r2 ; b1 = [i7+i11 | i6+i10]
196 qsub16 r6, r9, r2 ; c1 = [i7-i11 | i6-i10]
/external/llvm/test/Transforms/LoopVectorize/
Dreverse_induction.ll17 %add.i7 = phi i64 [ %startval, %entry ], [ %add.i, %for.body ]
20 %add.i = add i64 %add.i7, -1
40 %add.i7 = phi i128 [ %startval, %entry ], [ %add.i, %for.body ]
43 %add.i = add i128 %add.i7, -1
64 %add.i7 = phi i16 [ %startval, %entry ], [ %add.i, %for.body ]
67 %add.i = add i16 %add.i7, -1
/external/libvpx/libvpx/vp8/common/x86/
Dloopfilter_block_sse2_x86_64.asm181 %define i7 [spp + 2 * stride3]
206 movdqa xmm10, i7
222 movdqa xmm1, i7
230 movdqa xmm1, i7
235 movdqa i7, xmm1
340 %define i7 [rsp + 112]
429 movdqa i7, xmm5
519 punpcklqdq xmm5, i7
520 punpckhqdq xmm15, i7
529 movdqa i7, xmm11
[all …]
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dintrinsic.ll100 %i7 = load i32, i32* %arrayidx7, align 4
101 %add4 = add i32 %i6, %i7
147 %i7 = load i32, i32* %arrayidx7, align 4
148 %add4 = add i32 %i6, %i7
192 %i7 = load i32, i32* %arrayidx7, align 4
193 %add4 = add i32 %i6, %i7
237 %i7 = load i32, i32* %arrayidx7, align 4
238 %add4 = add i32 %i6, %i7
282 %i7 = load i32, i32* %arrayidx7, align 4
283 %add4 = add i32 %i6, %i7
[all …]
/external/llvm/test/CodeGen/AArch64/
Daarch64-dynamic-stack-layout.ll22 ;extern "C" int novla_nodynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7,…
29 …odynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int…
36 ;extern "C" int novla_dynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, i…
43 ;extern "C" int novla_dynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7,…
51 ;extern "C" int vla_nodynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, i…
59 ;extern "C" int vla_nodynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7,…
67 ;extern "C" int vla_dynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int…
75 ;extern "C" int vla_dynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7, i…
86 …micrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i…
125 …crealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i…
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dcall-03.ll109 ; Test a function that returns a value truncated from i64 to i7.
110 define i7 @f9() {
114 %trunc = trunc i64 %res to i7
115 ret i7 %trunc
/external/llvm/test/CodeGen/PowerPC/
Dstdux-constuse.ll18 %i7 = getelementptr i64, i64* %i6, i64 300000
22 store i64 %add, i64* %i7, align 32
/external/llvm/test/CodeGen/R600/
Dsi-vector-hang.ll55 %arrayidx.i.i7 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 4
56 %24 = load i8, i8 addrspace(1)* %arrayidx.i.i7, align 1
88 %arrayidx.i.i7.i = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 6
89 store i8 %38, i8 addrspace(1)* %arrayidx.i.i7.i, align 1
/external/llvm/test/CodeGen/ARM/
Difcvt-branch-weight-bug.ll34 %tobool.i.i7 = icmp eq i32 undef, 0
35 br i1 %tobool.i.i7, label %for.cond.backedge, label %cond.false.i

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