/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-basic-a64-undefined.txt | 16 # ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrNEON.td | 3870 let Inst{21-19} = 0b001; // imm6 = 001xxx 3874 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3878 let Inst{21} = 0b1; // imm6 = 1xxxxx 3882 // imm6 = xxxxxx 3887 let Inst{21-19} = 0b001; // imm6 = 001xxx 3891 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3895 let Inst{21} = 0b1; // imm6 = 1xxxxx 3899 // imm6 = xxxxxx 3907 let Inst{21-19} = 0b001; // imm6 = 001xxx 3911 let Inst{21-20} = 0b01; // imm6 = 01xxxx [all …]
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D | ARMInstrFormats.td | 217 // other shift immediates. The imm6 field is encoded like so: 220 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 221 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 222 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 223 // 64 64 - <imm> is encoded in imm6<5:0>
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/external/valgrind/VEX/priv/ |
D | host_arm64_defs.h | 221 UInt imm6; /* 1 .. 63 */ member 230 extern ARM64RI6* ARM64RI6_I6 ( UInt imm6 );
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D | host_arm_isel.c | 3123 UInt imm6; in iselNeon64Expr_wrk() local 3129 imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; in iselNeon64Expr_wrk() 3130 vassert(imm6 <= 32 && imm6 > 0); in iselNeon64Expr_wrk() 3131 imm6 = 64 - imm6; in iselNeon64Expr_wrk() 3139 addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, False)); in iselNeon64Expr_wrk() 5234 UInt imm6; in iselNeonExpr_wrk() local 5240 imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; in iselNeonExpr_wrk() 5241 vassert(imm6 <= 32 && imm6 > 0); in iselNeonExpr_wrk() 5242 imm6 = 64 - imm6; in iselNeonExpr_wrk() 5250 addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, True)); in iselNeonExpr_wrk()
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D | guest_arm64_toIR.c | 2693 UInt imm6 = INSN(15,10); in dis_ARM64_data_processing_immediate() local 2699 if (!is64 && imm6 >= 32) in dis_ARM64_data_processing_immediate() 2708 if (imm6 == 0) { in dis_ARM64_data_processing_immediate() 2712 vassert(imm6 > 0 && imm6 < szBits); in dis_ARM64_data_processing_immediate() 2714 binop(mkSHL(ty), mkexpr(srcHi), mkU8(szBits-imm6)), in dis_ARM64_data_processing_immediate() 2715 binop(mkSHR(ty), mkexpr(srcLo), mkU8(imm6)))); in dis_ARM64_data_processing_immediate() 2720 nameIRegOrZR(is64,nn), nameIRegOrZR(is64,mm), imm6); in dis_ARM64_data_processing_immediate() 2813 UInt imm6 = INSN(15,10); in dis_ARM64_data_processing_register() local 2819 if ((!is64 && imm6 > 31) || sh == BITS2(1,1)) { in dis_ARM64_data_processing_register() 2824 IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, False); in dis_ARM64_data_processing_register() [all …]
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D | host_arm64_defs.c | 423 ARM64RI6* ARM64RI6_I6 ( UInt imm6 ) { in ARM64RI6_I6() argument 426 ri6->ARM64ri6.I6.imm6 = imm6; in ARM64RI6_I6() 427 vassert(imm6 > 0 && imm6 < 64); in ARM64RI6_I6() 440 vex_printf("#%u", ri6->ARM64ri6.I6.imm6); in ppARM64RI6() 3387 UInt sh = argR->ARM64ri6.I6.imm6; in emit_ARM64Instr()
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D | host_arm64_isel.c | 1248 vassert(ri->ARM64ri6.I6.imm6 < 64); in iselIntExpr_RI6() 1249 vassert(ri->ARM64ri6.I6.imm6 > 0); in iselIntExpr_RI6()
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D | guest_arm_toIR.c | 5908 UInt imm6 = (theInstr >> 16) & 0x3f; in dis_neon_data_2reg_and_shift() local 5922 tmp = (L << 6) | imm6; in dis_neon_data_2reg_and_shift() 5925 shift_imm = 64 - imm6; in dis_neon_data_2reg_and_shift() 5928 shift_imm = 64 - imm6; in dis_neon_data_2reg_and_shift() 5931 shift_imm = 32 - imm6; in dis_neon_data_2reg_and_shift() 5934 shift_imm = 16 - imm6; in dis_neon_data_2reg_and_shift()
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/external/llvm/test/MC/Disassembler/ARM/ |
D | invalid-armv7.txt | 357 # imm6=0b0xxxxx -> UNDEFINED
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrFormats.td | 549 // {5-0} - imm6 571 // {5-0} - imm6 593 // {5-0} - imm6: #0, #8, #16, or #24 602 // {5-0} - imm6: #0 or #8 625 // {5-0} - imm6: #0 or #12
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/external/lldb/source/Plugins/Instruction/ARM/ |
D | EmulateInstructionARM.cpp | 2283 uint32_t imm6 = Bits32(opcode, 21, 16); in EmulateB() local 2287 uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); in EmulateB()
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