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Searched refs:immr (Results 1 – 13 of 13) sorted by relevance

/external/v8/src/arm64/
Dassembler-arm64-inl.h1075 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) {
1076 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
1077 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
1079 DCHECK(is_uint6(immr));
1080 return immr << ImmR_offset;
1093 Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) {
1095 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
1096 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
1098 return immr << ImmRotate_offset;
Dassembler-arm64.h1199 unsigned immr,
1205 unsigned immr,
1211 unsigned immr,
1822 inline static Instr ImmR(unsigned immr, unsigned reg_size);
1824 inline static Instr ImmRotate(unsigned immr, unsigned reg_size);
Dassembler-arm64.cc1279 unsigned immr, in bfm() argument
1284 ImmR(immr, rd.SizeInBits()) | in bfm()
1292 unsigned immr, in sbfm() argument
1297 ImmR(immr, rd.SizeInBits()) | in sbfm()
1305 unsigned immr, in ubfm() argument
1310 ImmR(immr, rd.SizeInBits()) | in ubfm()
/external/llvm/test/CodeGen/AArch64/
Dbitfield-insert-0.ll3 ; The encoding of lsb -> immr in the CGed bitfield instructions was wrong at one
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp112 int64_t immr = Op2.getImm(); in printInst() local
114 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
118 ((imms + 1 == immr))) { in printInst()
123 shift = immr; in printInst()
126 shift = immr; in printInst()
129 shift = immr; in printInst()
132 shift = immr; in printInst()
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-basic-a64-undefined.txt20 # UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
/external/vixl/src/vixl/a64/
Dassembler-a64.h1343 unsigned immr,
1349 unsigned immr,
1355 unsigned immr,
3813 static Instr ImmR(unsigned immr, unsigned reg_size) { in ImmR() argument
3814 VIXL_ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) || in ImmR()
3815 ((reg_size == kWRegSize) && is_uint5(immr))); in ImmR()
3817 VIXL_ASSERT(is_uint6(immr)); in ImmR()
3818 return immr << ImmR_offset; in ImmR()
3829 static Instr ImmRotate(unsigned immr, unsigned reg_size) { in ImmRotate() argument
3831 VIXL_ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) || in ImmRotate()
[all …]
Dmacro-assembler-a64.h977 unsigned immr, in Bfm() argument
983 bfm(rd, rn, immr, imms); in Bfm()
1707 unsigned immr, in Sbfm() argument
1713 sbfm(rd, rn, immr, imms); in Sbfm()
1973 unsigned immr, in Ubfm() argument
1979 ubfm(rd, rn, immr, imms); in Ubfm()
Dassembler-a64.cc1057 unsigned immr, in bfm() argument
1062 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in bfm()
1068 unsigned immr, in sbfm() argument
1073 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in sbfm()
1079 unsigned immr, in ubfm() argument
1084 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in ubfm()
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h295 unsigned immr = (val >> 6) & 0x3f; in decodeLogicalImmediate() local
302 unsigned R = immr & (size - 1); in decodeLogicalImmediate()
/external/vixl/doc/
Dsupported-instructions.md152 unsigned immr,
1023 unsigned immr,
1336 unsigned immr,
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1846 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1847 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1851 bits<6> immr;
1856 let Inst{21-16} = immr;
1866 // imms<5> and immr<5> must be zero, else ReservedValue().
1879 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
1881 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1885 bits<6> immr;
1890 let Inst{21-16} = immr;
1900 // imms<5> and immr<5> must be zero, else ReservedValue().
/external/valgrind/VEX/priv/
Dguest_arm64_toIR.c2329 ULong immN, ULong imms, ULong immr, Bool immediate, in dbm_DecodeBitMasks() argument
2334 vassert(immr < (1ULL << 6)); in dbm_DecodeBitMasks()
2354 ULong R = immr & levels; in dbm_DecodeBitMasks()