Searched refs:is128BitVector (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 135 bool is128BitVector() const { in is128BitVector() function
136 return isSimple() ? V.is128BitVector() : isExtended128BitVector(); in is128BitVector()
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| D | MachineValueType.h | 224 bool is128BitVector() const { in is128BitVector() function
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.h | 100 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
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| D | AArch64ISelLowering.cpp | 1750 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in addRequiredExtensionForVectorMULL()
1853 assert(VT.is128BitVector() && VT.isInteger() && in LowerMUL()
2132 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
6158 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
7639 if (!VT.is128BitVector()) { in performAddSubLongCombine()
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| D | AArch64FastISel.cpp | 2861 VT.is128BitVector()) in fastLowerArguments()
2907 } else if (VT.is128BitVector()) { in fastLowerArguments()
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| D | AArch64ISelDAGToDAG.cpp | 1025 } else if (VT.is128BitVector()) { in SelectIndexedLoad()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 671 if (!Ty.is128BitVector()) in performORCombine()
985 if (Ty.is128BitVector() && Ty.isInteger()) { in performVSELECTCombine()
1042 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { in performXORCombine()
2276 if (!VecTy.is128BitVector()) in lowerEXTRACT_VECTOR_ELT()
2328 if (!Subtarget.hasMSA() || !ResTy.is128BitVector()) in lowerBUILD_VECTOR()
2699 if (!ResTy.is128BitVector()) in lowerVECTOR_SHUFFLE()
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| D | MipsSEISelDAGToDAG.cpp | 882 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector()) in selectNode()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 855 if (!VT.is128BitVector()) in X86TargetLowering()
898 if (!VT.is128BitVector()) in X86TargetLowering()
1200 if (VT.is128BitVector()) { in X86TargetLowering()
1387 if (VT.is128BitVector() || VT.is256BitVector()) { in X86TargetLowering()
1619 if (VT.is256BitVector() || VT.is128BitVector()) { in getSetCCResultType()
2338 else if (RegVT.is128BitVector()) in LowerFormalArguments()
2813 if (RegVT.is128BitVector()) { in LowerCall()
3950 if (VT.is128BitVector()) { // SSE in getZeroVector()
4075 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!"); in Insert128BitVector()
4164 } else if (VT.is128BitVector()) { in getOnesVector()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4060 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; in getZeroVector()
4985 DAG, VmovVT, VT.is128BitVector(), in LowerBUILD_VECTOR()
4996 DAG, VmovVT, VT.is128BitVector(), in LowerBUILD_VECTOR()
5329 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
5661 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && in LowerCONCAT_VECTORS()
5779 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in AddRequiredExtensionForVMULL()
5883 assert(VT.is128BitVector() && VT.isInteger() && in LowerMUL()
8108 if (VT.is64BitVector() || VT.is128BitVector()) in PerformMULCombine()
8202 DAG, VbicVT, VT.is128BitVector(), in PerformANDCombine()
8245 DAG, VorrVT, VT.is128BitVector(), in PerformORCombine()
[all …]
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| D | ARMISelDAGToDAG.cpp | 2431 if (!VT.is128BitVector() || N->getNumOperands() != 2) in SelectConcatVector()
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