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Searched refs:isCall (Results 1 – 25 of 89) sorted by relevance

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/external/llvm/include/llvm/IR/
DCallSite.h74 bool isCall() const { return I.getInt(); } in isCall() function
167 return isCall() && cast<CallInst>(getInstruction())->isMustTailCall(); in isMustTailCall()
172 return isCall() && cast<CallInst>(getInstruction())->isTailCall(); in isTailCall()
177 return isCall() \
183 if (isCall()) \
337 if (isCall()) in getArgumentEndOffset()
344 if (isCall()) // Skip Callee in getCallee()
/external/llvm/lib/Target/X86/
DX86VZeroUpper.cpp128 if (MI->isCall() && MO.isRegMask() && !clobbersAllYmmRegs(MO)) in hasYmmReg()
143 assert(MI->isCall() && "Can only be called on call instructions."); in callClobbersAnyYmmReg()
184 bool isControlFlow = MI->isCall() || MI->isReturn(); in processBasicBlock()
207 if (MI->isCall() && !callClobbersAnyYmmReg(MI)) in processBasicBlock()
DX86PadShortFunction.cpp132 assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() && in runOnMachineFunction()
189 if (MI->isReturn() && !MI->isCall()) { in cyclesUntilReturn()
DX86InstrControl.td174 let isCall = 1 in
228 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
260 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
281 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
/external/llvm/include/llvm/MC/
DMCInstrAnalysis.h50 virtual bool isCall(const MCInst &Inst) const { in isCall() function
51 return Info->get(Inst.getOpcode()).isCall(); in isCall()
DMCInstrDesc.h236 bool isCall() const { in isCall() function
291 if (isBranch() || isCall() || isReturn() || isIndirectBranch()) in mayAffectControlFlow()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp94 SU->isCall = Old->isCall; in Clone()
358 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) in BuildSchedUnits()
359 NodeSUnit->isCall = true; in BuildSchedUnits()
376 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) in BuildSchedUnits()
377 NodeSUnit->isCall = true; in BuildSchedUnits()
383 if (NodeSUnit->isCall) in BuildSchedUnits()
DScheduleDAGRRList.cpp644 if (SU->isCall) in AdvancePastStalls()
692 if (SU->isCall) { in EmitNode()
2421 if (left->isCall && right->isCallOp) { in BURRSort()
2425 if (right->isCall && left->isCallOp) { in BURRSort()
2435 if (left->isCall || right->isCall) { in BURRSort()
2475 if ((left->isCall && RPriority > 0) || (right->isCall && LPriority > 0)) in BURRSort()
2480 !(left->isCall || right->isCall)) { in BURRSort()
2545 if (left->isCall || right->isCall) in operator ()()
2611 if (left->isCall || right->isCall) in operator ()()
/external/llvm/lib/Target/Mips/
DMipsDelaySlotFiller.cpp304 if (MI.isCall()) in init()
316 assert(MI.isCall()); in setCallerSaved()
594 DSI->isCall()) { in runOnMachineBasicBlock()
654 assert((!I->isCall() && !I->isReturn() && !I->isBranch()) && in searchRange()
710 if (DisableForwardSearch || !Slot->isCall()) in searchForward()
855 return (Candidate.isTerminator() || Candidate.isCall() || in terminateSearch()
DMipsOptimizePICCall.cpp248 if (!MI.isCall()) in isCallViaRegister()
/external/llvm/include/llvm/CodeGen/
DScheduleDAG.h294 bool isCall : 1; // Is a function call.
329 NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
345 NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
360 NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp65 bool isCall(const MCInst &MI, bool *IsIndirectCall) { in isCall() function in __anon39d610e60111::MipsNaClELFStreamer
171 if (isCall(Inst, &IsIndirectCall)) { in EmitInstruction()
/external/llvm/lib/Target/Hexagon/
DHexagonVLIWPacketizer.cpp380 return (MI->getDesc().isTerminator() || MI->getDesc().isCall()); in IsControlFlow()
1030 (IsDirectJump(J) || MCIDJ.isCall() || QII->isDeallocRet(J))) { in isLegalToPacketizeTogether()
1035 (IsDirectJump(I) || MCIDI.isCall() || QII->isDeallocRet(I))) { in isLegalToPacketizeTogether()
1043 (MCIDJ.isBranch() || MCIDJ.isCall() || MCIDJ.isBarrier())) { in isLegalToPacketizeTogether()
1099 if (PacketSU->getInstr()->getDesc().isCall()) { in isLegalToPacketizeTogether()
1171 if ((MCIDI.isCall() || MCIDI.isReturn()) && in isLegalToPacketizeTogether()
1200 !MCIDJ.isCall() && in isLegalToPacketizeTogether()
DHexagonInstrInfoV3.td24 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicable = 1,
39 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicated = 1,
67 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
DHexagonMachineScheduler.cpp30 if (SUnits[su].getInstr()->isCall()) in postprocessDAG()
330 if (!isTop() && SU->isCall) { in bumpNode()
/external/llvm/lib/Target/ARM/
DARMOptimizeBarriersPass.cpp46 MI->isCall() || in CanMovePastDMB()
/external/llvm/lib/Target/Sparc/
DDelaySlotFiller.cpp194 if (slot->isCall()) in findDelayInstr()
339 if (!I->isCall()) in needsUnimp()
/external/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp217 (ExitMI->isCall() || ExitMI->isBarrier()); in addSchedBarrierDeps()
348 } else if (SU->isCall) { in addPhysRegDeps()
359 if (!I->SU->isCall) in addPhysRegDeps()
463 if (MI->isCall() || MI->hasUnmodeledSideEffects() || in isGlobalMemoryObject()
709 SU->isCall = MI->isCall(); in initSUnits()
DCriticalAntiDepBreaker.cpp167 bool Special = MI->isCall() || in PrescanInstruction()
589 if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
/external/llvm/test/CodeGen/X86/
Dtls-addr-non-leaf-function.ll13 ; a call when inspected by the analysis passes (it doesn't have the "isCall"
/external/llvm/lib/CodeGen/AsmPrinter/
DEHStreamer.cpp160 assert(MI->isCall() && "This should be a call instruction!"); in callToNoUnwindFunction()
237 if (MI.isCall()) in computeCallSiteTable()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp68 bool isCall = false);
642 bool isCall) { in parseSparcAsmOperand() argument
697 if (isCall && in parseSparcAsmOperand()
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td127 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
174 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
190 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
253 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
259 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
264 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
270 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
276 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
282 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
/external/llvm/utils/TableGen/
DCodeGenInstruction.h232 bool isCall : 1; variable
/external/llvm/lib/Transforms/Scalar/
DPlaceSafepoints.cpp185 if (CS.isCall()) { in needsStatepoint()
888 if (CS.isCall()) { in ReplaceWithStatepoint()

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