Searched refs:isLd (Results 1 – 3 of 3) sorted by relevance
| /external/valgrind/memcheck/tests/ |
| D | cond_ld_st.c | 354 int i, Bool isLd, const TestCase* tc ) in do_test_case_steer() argument
357 if (i == 0) { fn(i,isLd,tc); return; }; in do_test_case_steer()
359 if (i == 1) { fn(i,isLd,tc); return; }; in do_test_case_steer()
361 if (i == 2) { fn(i,isLd,tc); return; }; in do_test_case_steer()
363 if (i == 3) { fn(i,isLd,tc); return; }; in do_test_case_steer()
365 if (i == 4) { fn(i,isLd,tc); return; }; in do_test_case_steer()
367 if (i == 5) { fn(i,isLd,tc); return; }; in do_test_case_steer()
369 if (i == 6) { fn(i,isLd,tc); return; }; in do_test_case_steer()
371 if (i == 7) { fn(i,isLd,tc); return; }; in do_test_case_steer()
373 if (i == 8) { fn(i,isLd,tc); return; }; in do_test_case_steer()
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1262 bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD; in MergeBaseUpdateLoadStore() local
1329 .addReg(Base, getKillRegState(isLd ? BaseKill : false)) in MergeBaseUpdateLoadStore()
1331 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
1333 } else if (isLd) { in MergeBaseUpdateLoadStore()
1494 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8; in FixInvalidRegPairOp() local
1495 bool EvenDeadKill = isLd ? in FixInvalidRegPairOp()
1498 bool OddDeadKill = isLd ? in FixInvalidRegPairOp()
1512 unsigned NewOpc = (isLd) in FixInvalidRegPairOp()
1515 if (isLd) { in FixInvalidRegPairOp()
1519 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
[all …]
|
| D | ARMInstrFormats.td | 631 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
641 let Inst{20} = isLd;
644 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
654 let Inst{20} = isLd; // L bit
|