Searched refs:isMClass (Results 1 – 7 of 7) sorted by relevance
403 bool isMClass() const { return ARMProcClass == MClass; } in isMClass() function408 return isThumb1Only() && isMClass(); in isV6M()
75 if (STI.isMClass()) { in getCalleeSavedRegs()
540 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP()) in getArchForCPU()611 } else if (STI.isMClass()) { in emitAttributes()
699 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()707 if (Subtarget.isMClass()) in copyFromCPSR()720 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()725 if (Subtarget.isMClass()) in copyToCPSR()
1171 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4); in shouldAlignPointerArgs()1727 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass()); in LowerCall()1763 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass()); in LowerCall()2276 !Subtarget->isMClass()) { in LowerReturn()2739 if (Subtarget->isMClass()) { in LowerATOMIC_FENCE()11023 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain; in makeDMB()11085 return (Size == 64) && !Subtarget->isMClass(); in shouldExpandAtomicStoreInIR()11097 return (Size == 64) && !Subtarget->isMClass(); in shouldExpandAtomicLoadInIR()11105 return (Size <= (Subtarget->isMClass() ? 32U : 64U)) in shouldExpandAtomicRMWInIR()
264 def IsMClass : Predicate<"Subtarget->isMClass()">,266 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
287 bool isMClass() const { in isMClass() function in __anonef5d38c20111::ARMAsmParser4009 if (isMClass()) { in parseMSRMaskOperand()5771 } else if (Mnemonic == "cps" && isMClass()) { in ParseInstruction()6344 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) in validateInstruction()