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Searched refs:isRegMask (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/lib/CodeGen/
DLivePhysRegs.cpp47 } else if (O->isRegMask()) in stepBackward()
83 } else if (O->isRegMask()) in stepForward()
DRegisterScavenging.cpp113 if (MO.isRegMask()) { in determineKillsAndDefs()
315 if (MO.isRegMask()) in findSurvivorReg()
DDeadMachineInstructionElim.cpp154 } else if (MO.isRegMask()) { in runOnMachineFunction()
DCriticalAntiDepBreaker.cpp251 if (MO.isRegMask()) in ScanInstruction()
349 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg)) in isNewRegClobberedByRefs()
DMachineCSE.cpp191 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) in isPhysDefTriviallyDead()
318 if (MO.isRegMask()) in PhysRegDefsReach()
DMachineInstrBundle.cpp292 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) in analyzePhysReg()
DMachineCopyPropagation.cpp243 if (MO.isRegMask()) in CopyPropagateBlock()
DMachineInstr.cpp709 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || in addOperand()
1182 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) in findRegisterDefOperandIdx()
1495 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyImplicitOps()
1896 if (MO.isRegMask()) { in setPhysRegsDeadExcept()
DVirtRegMap.cpp346 if (MO.isRegMask()) in rewrite()
DLiveIntervalAnalysis.cpp227 if (!MO->isRegMask()) in computeRegMasks()
931 if (MO->isRegMask()) in updateAllRanges()
DEarlyIfConversion.cpp230 if (MO->isRegMask()) { in canSpeculateInstrs()
DBranchFolding.cpp1659 if (MO.isRegMask()) in findHoistingInsertPosAndDeps()
1771 if (MO.isRegMask()) { in HoistCommonCodeInSuccs()
DLiveVariables.cpp517 if (MO.isRegMask()) { in runOnInstr()
DRegAllocFast.cpp923 if (MO.isRegMask()) { in AllocateBasicBlock()
DMachineLICM.cpp445 if (MO.isRegMask()) { in ProcessMI()
DScheduleDAGInstrs.cpp1144 if (MO.isRegMask()) in fixupKills()
/external/llvm/lib/Target/X86/
DX86VZeroUpper.cpp128 if (MI->isCall() && MO.isRegMask() && !clobbersAllYmmRegs(MO)) in hasYmmReg()
146 if (!MO.isRegMask()) in callClobbersAnyYmmReg()
/external/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp510 if (J.isRegMask()) in scavengeRegister()
566 } else if (U.isRegMask()) { in colorChain()
702 } else if (MO.isRegMask()) { in maybeKillChain()
DAArch64CollectLOH.cpp325 if (!MO.isRegMask()) in initReachingDef()
DAArch64LoadStoreOptimizer.cpp448 if (MO.isRegMask()) in trackRegDefsUses()
/external/llvm/include/llvm/CodeGen/
DMachineOperand.h251 bool isRegMask() const { return OpKind == MO_RegisterMask; } in isRegMask() function
485 assert(isRegMask() && "Wrong MachineOperand accessor"); in getRegMask()
/external/llvm/lib/Target/PowerPC/
DPPCCTRLoops.cpp580 } else if (MO.isRegMask()) { in clobbersCTR()
DPPCInstrInfo.cpp1351 } else if (MO.isRegMask()) { in DefinesPredicate()
/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp475 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) { in saveScavengerRegister()
DARMBaseInstrInfo.cpp512 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || in DefinesPredicate()
2498 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { in optimizeCompareInstr()

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