Searched refs:isSEXTLoad (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 629 bool isSEXTLoad, SDValue &Base, in getIndexedAddressParts() argument
674 bool isSEXTLoad = false; in getPostIndexedAddressParts() local
678 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPostIndexedAddressParts()
689 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, in getPostIndexedAddressParts()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 5735 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) in isSignExtended()
10216 bool isSEXTLoad, SDValue &Base, in getARMIndexedAddressParts() argument
10222 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { in getARMIndexedAddressParts()
10275 bool isSEXTLoad, SDValue &Base, in getT2IndexedAddressParts() argument
10312 bool isSEXTLoad = false; in getPreIndexedAddressParts() local
10316 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPreIndexedAddressParts()
10326 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, in getPreIndexedAddressParts()
10329 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, in getPreIndexedAddressParts()
10351 bool isSEXTLoad = false; in getPostIndexedAddressParts() local
10355 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPostIndexedAddressParts()
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 2107 inline bool isSEXTLoad(const SDNode *N) {
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3084 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && in visitAND()
5632 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && in visitSIGN_EXTEND()
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