| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.cpp | 174 Entry.isSExt = false; in EmitTargetCodeForMemset()
186 Entry.isSExt = true; in EmitTargetCodeForMemset()
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| D | ARMFastISel.cpp | 2134 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in SelectRet()
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| D | ARMISelLowering.cpp | 6177 Entry.isSExt = false; in LowerFSINCOS()
6184 Entry.isSExt = false; in LowerFSINCOS()
10777 Entry.isSExt = isSigned; in LowerDivRem()
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| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.h | 66 bool isSExt() const { return Flags & SExt; } in isSExt() function
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| D | TargetLowering.h | 2222 bool isSExt : 1; member
2232 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.td | 13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2433 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
2436 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2442 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; in Select()
2448 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2453 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; in Select()
2468 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
2471 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2479 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; in Select()
2485 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
2490 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; in Select()
[all …]
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| D | PPCISelLowering.cpp | 2831 if (Flags.isSExt()) in extendArgForPPC64()
4727 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4()
5289 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 731 bool isSExt = true; in getCopyFromRegs() local
734 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 in getCopyFromRegs()
736 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 in getCopyFromRegs()
738 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 in getCopyFromRegs()
740 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 in getCopyFromRegs()
742 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 in getCopyFromRegs()
744 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 in getCopyFromRegs()
746 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 in getCopyFromRegs()
748 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 in getCopyFromRegs()
754 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
[all …]
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| D | LegalizeDAG.cpp | 2055 Entry.isSExt = isSigned; in ExpandLibCall()
2103 Entry.isSExt = isSigned; in ExpandLibCall()
2137 Entry.isSExt = isSigned; in ExpandChainLibCall()
2264 Entry.isSExt = isSigned; in ExpandDivRemLibCall()
2273 Entry.isSExt = isSigned; in ExpandDivRemLibCall()
2369 Entry.isSExt = false; in ExpandSinCosLibCall()
2377 Entry.isSExt = false; in ExpandSinCosLibCall()
2385 Entry.isSExt = false; in ExpandSinCosLibCall()
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| D | LegalizeTypes.cpp | 1076 Entry.isSExt = isSigned; in ExpandChainLibCall()
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| D | TargetLowering.cpp | 72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt); in setAttributes()
99 Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned); in makeLibCall()
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| D | LegalizeIntegerTypes.cpp | 2376 Entry.isSExt = true; in ExpandIntRes_XMULO()
2384 Entry.isSExt = true; in ExpandIntRes_XMULO()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1277 if (Outs[OIdx].Flags.isSExt()) in LowerCall()
1288 else if (Outs[OIdx].Flags.isSExt()) in LowerCall()
2149 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
2276 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 123 if (ArgFlags.isSExt()) in CC_Hexagon_VarArg()
161 if (ArgFlags.isSExt()) in CC_Hexagon()
242 if (ArgFlags.isSExt()) in RetCC_Hexagon()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1023 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1029 if (Outs[0].Flags.isSExt()) in X86SelectRet()
2855 if (Flags.isSExt()) in fastLowerCall()
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| D | X86ISelLowering.cpp | 15988 Entry.isSExt = false; in LowerWin64_i128OP()
17143 Entry.isSExt = false; in LowerFSINCOS()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1242 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()
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| D | MipsISelLowering.cpp | 2340 if (ArgFlags.isSExt()) in CC_MipsO32()
2352 if (ArgFlags.isSExt()) in CC_MipsO32()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 313 if (ArgFlags.isSExt()) in AnalyzeArguments()
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 523 Offset, Ins[i].Flags.isSExt()); in LowerFormalArguments()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3726 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()
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| D | AArch64ISelLowering.cpp | 1694 Entry.isSExt = false; in LowerFSINCOS()
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