Searched refs:isTypeDesirableForOp (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 636 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
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| D | X86ISelLowering.cpp | 23941 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { in isTypeDesirableForOp() function in X86TargetLowering
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 647 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
986 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
1340 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
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| D | DAGCombiner.cpp | 988 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntBinOp()
1046 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntShiftOp()
1090 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteExtend()
1119 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteLoad()
2568 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || in SimplifyBinOpWithSameOpcodeHands()
4550 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
6686 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { in visitTRUNCATE()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 2180 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { in isTypeDesirableForOp() function
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