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/external/llvm/lib/Target/ARM/
DARMInstrNEON.td267 // Register list of one D register, with byte lane subscripting.
277 // ...with half-word lane subscripting.
287 // ...with word lane subscripting.
298 // Register list of two D registers with byte lane subscripting.
308 // ...with half-word lane subscripting.
318 // ...with word lane subscripting.
328 // Register list of two Q registers with half-word lane subscripting.
338 // ...with word lane subscripting.
350 // Register list of three D registers with byte lane subscripting.
360 // ...with half-word lane subscripting.
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/external/vixl/test/
Dtest-simulator-a64.cc1286 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpNEON() local
1287 unsigned index = lane + (iteration * vd_lane_count); in Test1OpNEON()
1309 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpNEON() local
1310 unsigned output_index = (n * vd_lane_count) + lane; in Test1OpNEON()
1327 for (unsigned lane = 0; in Test1OpNEON() local
1328 lane < std::max(vd_lane_count, vn_lane_count); in Test1OpNEON()
1329 lane++) { in Test1OpNEON()
1330 unsigned output_index = (n * vd_lane_count) + lane; in Test1OpNEON()
1331 unsigned input_index_n = (first_index_n + lane) % inputs_n_length; in Test1OpNEON()
1477 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpAcrossNEON() local
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/external/llvm/test/CodeGen/AArch64/
Darm64-neon-simd-ldst-one.ll131 %lane = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer
132 ret <16 x i8> %lane
141 %lane = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> zeroinitializer
142 ret <8 x i16> %lane
151 %lane = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer
152 ret <4 x i32> %lane
161 %lane = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> zeroinitializer
162 ret <2 x i64> %lane
171 %lane = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer
172 ret <4 x float> %lane
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Dfp16-vector-load-store.ll43 ; Load to one lane of v4f16
53 ; Load to one lane of v8f16
81 ; Store from one lane of v4f16
91 ; Store from one lane of v8f16
286 ; NEON intrinsics - loads and stores to/from one lane
300 ; Load one lane of 2 x v4f16
309 ; Load one lane of 3 x v4f16
318 ; Load one lane of 4 x v4f16
327 ; Store one lane of 2 x v4f16
336 ; Store one lane of 3 x v4f16
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Darm64-build-vector.ll3 ; Check that building up a vector w/ only one non-zero lane initializes
22 ; copy for lane zero.
Darm64-neon-2velem.ll386 %lane = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> <i32 1, i32 1>
387 %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
398 %lane = shufflevector <2 x float> %v, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
399 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %lane, <4 x float> %b, <4 x float> %a)
410 %lane = shufflevector <4 x float> %v, <4 x float> undef, <2 x i32> <i32 3, i32 3>
411 %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
420 %lane = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
421 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %lane, <4 x float> %b, <4 x float> %a)
431 %lane = shufflevector <2 x float> %sub, <2 x float> undef, <2 x i32> <i32 1, i32 1>
432 %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
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Darm64-ld1.ll924 %lane = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer
925 %tmp3 = bitcast <2 x i32> %lane to <8 x i8>
1000 %lane = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
1001 ret <4 x float> %lane
1012 %lane = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
1013 ret <2 x float> %lane
1024 %lane = shufflevector <2 x double> %tmp1, <2 x double> undef, <2 x i32> zeroinitializer
1025 ret <2 x double> %lane
1036 %lane = shufflevector <1 x double> %tmp1, <1 x double> undef, <1 x i32> zeroinitializer
1037 ret <1 x double> %lane
/external/llvm/test/CodeGen/ARM/
D2012-05-04-vmov.ll14 ; vmov.32 should not be used to get a lane:
15 ; vmov.32 <dst>, <src>[<lane>].
16 ; but vmov.32 <dst>[<lane>], <src> is fine.
Da15-partial-update.ll6 ; to write the lane 1 of a D register containing the value of
Dcoalesce-subregs.ll71 ; This function has lane insertions that span basic blocks.
120 ; This function inserts a lane into a fully defined vector.
121 ; The destination lane isn't read, so the subregs can coalesce.
152 ; It is inserting the %add value into a dead lane, but %add causes interference
153 ; in the entry block, and we don't do dead lane checks across basic blocks.
Dvget_lane.ll218 ; The llvm extractelement instruction does not require that the lane number
219 ; be an immediate constant. Make sure a variable lane number is handled.
/external/llvm/docs/
DBigEndianNEON.rst22 This trivial C function takes a vector of four ints and sets the zero'th lane to the value "42"::
61 …use of the byte swapping the lane indices end up being swapped! The zero'th item as laid out in me…
95 Use of ``LDR`` would break this lane ordering property. This doesn't preclude the use of ``LDR``, b…
97 1. Insert a ``REV`` instruction to reverse the lane order after every ``LDR``.
98 …hat rely on lane layout, and for every access to an individual lane (``insertelement``/``extractel…
109 …re not - the lane size is encoded within them. This is important across an ABI boundary, because i…
126 … should be undefined. But there may be functions that are agnostic to the lane layout of the vecto…
128 So to preserve ABI compatibility, we need to use the ``LDR`` lane layout across function calls.
133 …128-bit aligned, whereas ``LD1`` only requires it to be as aligned as the lane size. If we canonic…
152 …issue with lane ordering, it was decided, would have to change target-agnostic compiler passes and…
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/external/llvm/test/CodeGen/Thumb2/
D2013-03-02-vduplane-nonconstant-source-index.ll3 define void @bar(<4 x i32>* %p, i32 %lane, <4 x i32> %phitmp) nounwind {
8 %val = extractelement <4 x i32> %phitmp, i32 %lane
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc667 for (int lane = leftmost_lane; lane >= rightmost_lane; lane--) { in PrintVRegisterFPHelper() local
669 (lane_size_in_bytes == kSRegSizeInBytes) ? vreg(code).Get<float>(lane) in PrintVRegisterFPHelper()
670 : vreg(code).Get<double>(lane); in PrintVRegisterFPHelper()
762 unsigned lane) { in PrintVRead() argument
769 GetPrintRegLaneCount(format), lane); in PrintVRead()
793 unsigned lane) { in PrintVWrite() argument
805 PrintVRegisterRawHelper(reg_code, reg_size, lane_size * lane); in PrintVWrite()
807 PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane); in PrintVWrite()
3268 int lane = instr->NEONLSIndex(index_shift); in NEONLoadStoreSingleStructHelper() local
3277 ld1(vf, vreg(rt), lane, addr); in NEONLoadStoreSingleStructHelper()
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Dsimulator-a64.h404 void Insert(int lane, T new_value) { in Insert() argument
405 VIXL_ASSERT(lane >= 0); in Insert()
407 (lane * sizeof(new_value))) <= kSizeInBytes); in Insert()
408 memcpy(&value_[lane * sizeof(new_value)], &new_value, sizeof(new_value)); in Insert()
414 T Get(int lane = 0) const {
416 VIXL_ASSERT(lane >= 0);
417 VIXL_ASSERT((sizeof(result) + (lane * sizeof(result))) <= kSizeInBytes);
418 memcpy(&result, &value_[lane * sizeof(result)], sizeof(result));
1260 PrintRegisterFormat format, unsigned lane);
1262 PrintRegisterFormat format, unsigned lane);
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Dmacro-assembler-a64.h2526 int lane, in Ld1() argument
2530 ld1(vt, lane, src); in Ld1()
2547 int lane, in Ld2() argument
2551 ld2(vt, vt2, lane, src); in Ld2()
2571 int lane, in Ld3() argument
2575 ld3(vt, vt2, vt3, lane, src); in Ld3()
2598 int lane, in Ld4() argument
2602 ld4(vt, vt2, vt3, vt4, lane, src); in Ld4()
2721 int lane, in St1() argument
2725 st1(vt, lane, dst); in St1()
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Dassembler-a64.cc2054 int lane, in ld2() argument
2059 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad2); in ld2()
2087 int lane, in ld3() argument
2092 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad3); in ld3()
2123 int lane, in ld4() argument
2128 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad4); in ld4()
2195 int lane, in st2() argument
2200 LoadStoreStructSingle(vt, lane, dst, NEONLoadStoreSingleStructStore2); in st2()
2218 int lane, in st3() argument
2223 LoadStoreStructSingle(vt, lane, dst, NEONLoadStoreSingleStructStore3); in st3()
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Dassembler-a64.h2723 int lane,
2738 int lane,
2756 int lane,
2777 int lane,
2995 int lane,
3006 int lane,
3019 int lane,
3034 int lane,
4198 uint32_t lane,
/external/llvm/include/llvm/IR/
DIntrinsicsARM.td424 // Vector load N-element structure to one lane.
426 // lane is assigned), the lane number, and the alignment.
463 // Vector store N-element structure from one lane.
464 // Source operands are: the address, the N vectors, the lane number, and
/external/tcpdump/
DAndroid.mk17 print-l2tp.c print-lane.c print-ldp.c print-lldp.c print-llc.c \
DMakefile.in87 print-l2tp.c print-lane.c print-ldp.c print-lldp.c print-llc.c \
155 lane.h \
DINSTALL.txt105 lane.h - ATM LANE definitions
179 print-lane.c - ATM LANE printer routines
/external/tcpdump/win32/prj/
DGNUmakefile91 ../../print-lane.o \
/external/llvm/test/CodeGen/X86/
Davx-cast.ll5 ; are simpler (no lane changes) and therefore will have equal or better
/external/vixl/doc/
Dsupported-instructions.md2468 One-element single structure load to one lane.
2471 int lane,
2523 Two-element single structure load to one lane.
2527 int lane,
2551 Three-element single structure load to one lane.
2556 int lane,
2582 Four-element single structure load to one lane.
2588 int lane,
3729 One-element single structure store from one lane.
3732 int lane,
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