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Searched refs:lanes (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td470 class TypedVecListAsmOperand<int count, int regsize, int lanes, string kind>
472 let Name = "TypedVectorList" # count # "_" # lanes # kind;
475 = "isTypedVectorList<" # count # ", " # lanes # ", '" # kind # "'>";
479 class TypedVecListRegOperand<RegisterClass Reg, int lanes, string kind>
480 : RegisterOperand<Reg, "printTypedVectorList<" # lanes # ", '"
DAArch64Schedule.td95 // Read the unwritten lanes of the VLD's destination registers.
DAArch64CallingConvention.td30 // their lanes are in a consistent order.
85 // their lanes are in a consistent order.
/external/mesa3d/src/gallium/drivers/nv50/codegen/
Dnv50_ir_emit_nv50.cpp602 code[1] = 0x00200000 | (i->lanes << 14); in emitLOAD()
619 code[1] = 0x00200000 | (i->lanes << 14); in emitLOAD()
759 code[1] |= (i->lanes << 14); in emitMOV()
1690 emitQUADOP(insn, insn->lanes, insn->subOp); in emitInstruction()
1759 if (i->join || i->lanes != 0xf || i->exit) in getMinEncodingSize()
Dnv50_ir.cpp573 lanes = 0xf; in init()
737 i->lanes = lanes; in clone()
Dnv50_ir_build_util.cpp265 quadop->lanes = l; in mkQuadop()
Dnv50_ir.h696 unsigned lanes : 4; variable
Dnv50_ir_lowering_nv50.cpp769 mov->lanes = 1 << l; in handleTXD()
Dnv50_ir_peephole.cpp2061 this->lanes != that->lanes || in isActionEqual()
/external/vixl/src/vixl/a64/
Dassembler-a64.h269 VRegister(unsigned code, unsigned size, unsigned lanes = 1)
270 : CPURegister(code, size, kVRegister), lanes_(lanes) { in CPURegister()
330 int lanes() const { in lanes() function
3999 switch (vd.lanes()) { in VFormat()
4007 switch (vd.lanes()) { in VFormat()
4020 if (vd.lanes() == 1) { in FPFormat()
4027 if (vd.lanes() == 2) { in FPFormat()
4033 VIXL_ASSERT((vd.lanes() == 4) && vd.Is128Bits()); in FPFormat()
4040 switch (vd.lanes()) { in LSVFormat()
4049 switch (vd.lanes()) { in LSVFormat()
[all …]
Dassembler-a64.cc1941 offset = (offset / vt.lanes()) * 1; break; in LoadStoreStructVerify()
1952 offset = (offset / vt.lanes()) * 2; break; in LoadStoreStructVerify()
1962 offset = (offset / vt.lanes()) * 3; break; in LoadStoreStructVerify()
1972 offset = (offset / vt.lanes()) * 4; break; in LoadStoreStructVerify()
3702 VIXL_ASSERT((0 <= index) && (index < vd.lanes())); in ext()
/external/llvm/test/CodeGen/X86/
Dvshift-4.ll16 ; shift1b can't use a packed shift but can shift lanes separately and shuffle back together
/external/clang/include/clang/Basic/
Darm_neon.td78 // - "H" - Halve the number of lanes in the type.
79 // - "D" - Double the number of lanes in the type.
94 // all lanes. The type of the vector is the base type of the intrinsic.
159 // is a width in bits to reverse. The lanes this maps to is determined
164 // mask0 - The initial sequence of lanes for shuffle ARG0
166 // mask0 - The initial sequence of lanes for shuffle ARG1
645 // E.3.16 Extract lanes from a vector
651 // E.3.17 Set lanes within a vector
663 // E.3.19 Set all lanes to same value
1074 // Set all lanes to same value
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_dc.s454 vdup.16 q12, d11[0] @3*dc + 2 (moved to all lanes)
/external/llvm/docs/
DBigEndianNEON.rst66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering.
109 … ``ST1``. ``LDR`` and ``STR`` are oblivious to the size of the individual lanes of a vector. ``LD1…
DLangRef.rst9760 …ed vector lane on or off. The memory addresses corresponding to the "off" lanes are not accessed. …
9779 …emory accesses to the masked-off lanes. The masked-off lanes in the result vector are taken from t…
9785 …e. The fourth is a pass-through value that is used to fill the masked-off lanes of the result. The…
9792 … same mask. However, using this intrinsic prevents exceptions on memory access to masked-off lanes.
9820 …k holds a bit for each vector lane, and is used to prevent memory accesses to the masked-off lanes.
9832 …ever, using this intrinsic prevents exceptions and data races on memory access to masked-off lanes.
/external/vixl/doc/
Dsupported-instructions.md2515 One-element single structure load to all lanes.
2542 Two-element single structure load to all lanes.
2572 Three-element single structure load to all lanes.
2605 Four-element single structure load to all lanes.
3776 Two-element single structure store from two lanes.
3795 Three-element single structure store from three lanes.
3816 Four-element single structure store from four lanes.
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt258 # A8.6.315 VLD3 (single 3-element structure to all lanes)
/external/mesa3d/src/gallium/drivers/nvc0/codegen/
Dnv50_ir_emit_nvc0.cpp1508 opc |= i->lanes << 5; in emitMOV()
1720 emitQUADOP(insn, insn->subOp, insn->lanes); in emitInstruction()
1780 if (i->op == OP_MOV && i->lanes != 0xf) { in getMinEncodingSize()
Dnv50_ir_lowering_nvc0.cpp791 mov->lanes = 1 << l; in handleManualTXD()
/external/llvm/test/CodeGen/ARM/
Dvmul.ll639 ; Look for doing a normal scalar FP load rather than an to-all-lanes load.
641 ; Then check that the vector multiply has folded the splat to all lanes
Dcoalesce-subregs.ll146 ; Coalesce vector lanes through phis.
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td197 // Register list of one D register, with "all lanes" subscripting.
206 // Register list of two D registers, with "all lanes" subscripting.
226 // Register list of three D registers, with "all lanes" subscripting.
246 // Register list of four D registers, with "all lanes" subscripting.
1364 // VLD1DUP : Vector Load (single element to all lanes)
1457 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1520 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1565 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
6541 // half the lanes available. Example:
6658 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
[all …]
/external/valgrind/none/tests/arm/
Dneon64.stdout.exp2007 ---- VLD1 (single element to all lanes) ----
2048 ---- VLD2 (2-elements to all lanes) ----
2086 ---- VLD3 (3-elements to all lanes) ----
2124 ---- VLD4 (4-elements to all lanes) ----
2293 ---- VLD1 (single element to all lanes) ----
2334 ---- VLD2 (2-elements to all lanes) ----
2372 ---- VLD3 (3-elements to all lanes) ----
2410 ---- VLD4 (4-elements to all lanes) ----
2579 ---- VLD1 (single element to all lanes) ----
2620 ---- VLD2 (2-elements to all lanes) ----
[all …]
/external/vixl/test/
Dtest-disasm-a64.cc2793 #define VLIST2(v) v, VRegister((v.code()+1)%32, v.size(), v.lanes())
2794 #define VLIST3(v) VLIST2(v), VRegister((v.code()+2)%32, v.size(), v.lanes())
2795 #define VLIST4(v) VLIST3(v), VRegister((v.code()+3)%32, v.size(), v.lanes())

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